Cost-effective SiC substrate manufacturing for power devices enabled by oxide-free wafer bonding

Silicon Carbide (SiC) power devices are seen as a game-changer in the automotive industry.

By Bernd Dielacher and Peter Kerepesi, EV Group

These advanced semiconductor devices offer superior device performance compared to conventional silicon-based devices. SiC as a material has a 3x wider bandgap, 10x higher breakdown voltage and a 5x higher thermal conductivity.

These properties ultimately translate into faster EV charging and more efficient and reliable automotive fleets. Large investments in new SiC wafer fabs underline the high interest from the automotive sector. However, SiC manufacturing processes are far from being as mature as silicon processes. Significant developments along the entire process chain are needed to pave the way for a SiC-based future of the EV industry.

Figure 1. SiC power MOSFET structure using a cost-effective engineered substrate (thin high quality monocrystalline SiC layer bonded on a less-expensive SiC substrate)

Challenges include the high costs associated with substrate manufacturing, the complex processing of SiC, limited economies of scale and overall yield issues. In particular, the substrate is a major concern as it accounts for the largest share of production costs. Many routes are currently being explored to address this issue including improvements of crystal growth or novel wafer slicing technologies. The transition to 8-inch manufacturing is also expected to reduce substrate costs. This will only pay off in the long term as the processes for this scale are more complex and still need to be established and optimized. Another way of reducing substrate costs is the use of wafer bonding to utilize the expensive high quality SiC material more efficiently.

Figure 2. EVG ComBond® - Automated High-Vacuum Wafer Bonding System

Wafer bonding is an established process in power device manufacturing, in particular temporary bonding is commonly used to support substrates during device thinning. Wafer bonding is not only used for device manufacturing, but also enables new types of substrates. In the case of SiC MOSFET power devices, the main structure is built into a thin epitaxial SiC layer, commonly grown on monocrystalline SiC wafers. SiC crystal growth defects can be minimized or eliminated during the epitaxial process and epi-layers can be efficiently electrically tuned by doping.

However, only high-quality monocrystalline SiC substrates provide the required electrical device performance but contribute significantly to the overall chip cost. Since this material is mainly required as a seed layer for the epitaxial process, using only a thin layer and substituting the bulk material with a polycrystalline or lower quality monocrystalline substrate is seen as a viable route to address this cost issue (Figure 1).

Such a process generally involves wafer bonding of the two materials as well as a method to produce a thin layer from the high-quality monocrystalline substrate and reuse the remaining substrate multiple times. Several methods for the thin layer generation have been demonstrated, including the well-known ion-implantation and splitting process. This article focuses on the wafer bonding process and presents the latest developments for this application using EVGs high-vacuum ComBond® cluster system.