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Technical Insight

Magazine Feature
This article was originally featured in the edition:
Issue 4 2022

Key criteria for Power MOSFETs in harsh linear mode applications

News

MOSFET devices are often thought of as the ‘workhorses’ of power electronics due to their wide-ranging applications. But as the experts at STMicroelectronics advise, key criteria are essential to follow when selecting devices for harsh linear mode applications.

By Giusy Gambino, STMicroelectronics, Catania, Italy

New advanced trench MOSFETs are increasingly requested with improved linear mode ruggedness to provide excellent performance in telecom, server and industrial applications. They play a key role in safety switches for battery insulation and power distribution, in-rush current limiters, electronic fuses, linear motor controllers, load switches and hot swap applications. These devices exhibit excellent performance in terms of conduction and switching figure of merit (FoM), offering an optimal efficiency and thermal behavior at high switching speed.

STMicroelectronics released new MOSFETs with a wide SOA capability able to outperform advanced planar technology in linear mode operation, being thermally stable for a wider range of operating conditions into the safe operating area (SOA). Depending on the gate-source voltage (VGS) levels at which the MOSFET is driven, different areas of the device with specific gate threshold voltage (Vth) and current gain values are involved in the drain current (ID) flow with a trade-off between linear mode and switching performance. With this improved design, the new trench power MOSFETs are ideal for rugged forward biased SOA (FBSOA) applications, where high-power levels with high drain-source voltage (VDS) drops are required, ensuring both a high surge current capability in linear mode and low static on-resistance (RDS(on)) in fully on conditions.

Linear Applications in Power Electronics
Linear mode operation is widely used in power electronics systems and applications that require safe and reliable devices with high ruggedness and thermal stability. High current handling for soft start under significant voltage drops, as well as limiting inrush peaks and any potential failure mechanism are all crucial for hot swap systems. In telecom applications, they are used to charge the bulk capacitor, which powers the entire loading system, such as server, rack and each load connected to the main power supply (Fig. 1).


Fig. 1. Hot swap system block diagram.

Since system maintenance is performed in most cases once it is permanently functional, by connecting the replaced parts to the rest of the live system, the capacitor may initially be completely discharged and then a huge current of up to hundreds of amperes can flow through the circuit.

Linear mode working conditions are also requested in fan motion control for heating, ventilation and air conditioning (HVAC) systems (Fig. 2).


Fig. 2. HVAC system block diagram.

According to the below motion control system, the VGS voltage of the MOSFET can be changed by tuning the duty cycle of the bipolar transistor driving voltage and then it is possible to control the current through the motor and its speed. The current is set by the equivalent resistance provided by the MOSFET when biased under FBSOA working conditions.

To meet the harsh requirements of linear mode applications, a dedicated MOSFET technology has to be considered with a special focus on the key parameters, such as the thermal coefficient, threshold voltage (Vth), transconductance (Gfs) and thermal resistance (Rth).

Thermal Coefficient
The key parameter to define the linear mode performance of a MOSFET is the thermal coefficient (TC) of the ID current. This coefficient represents the ability of the device to self-balance the current control at both high temperatures and voltages and can be calculated with the following equation (Eq. 1):

(1)

where: ID is the drain current and T the temperature of the MOSFET.

The heat developed inside the junction is due to the electrical power dissipation (PD) in linear mode (Eq. 2):

(2)

where: ZthJA is the junction-to-ambient thermal impedance.

When the temperature increases, the ID current changes according to the thermal coefficient and the device can manage the power until the failure point is reached. The maximum limit of the power is set by the following equation (Eq. 3):

(3)

The above equation shows that:

when TC is zero or negative, when the temperature increases, the drain current decreases, then the device works in thermal stability conditions;

when TC is positive, the device can work without failing if the ZthJA impedance is low enough to dissipate the heat generated by the applied power.

The thermal coefficient is a technology-dependent parameter, linked to the transfer characteristics of the power MOSFET (Fig. 3).


Fig. 3. Power MOSFET transfer characteristics at different temperatures.

The three transfer curves intersect at a crossing point, called zero temperature coefficient or zero tempco (ZTC):

For VGS = VGS(ZTC), the device current remains stable with temperature;

For VGS > VGS(ZTC), as the device temperature increases, the drain current tends to decrease, reaching conditions of thermal stability;

For VGS < VGS(ZTC) it is vice versa, as the device temperature increases. The drain current continues to increase thanks to the lower threshold voltage, which has a negative coefficient versus temperature. Consequently, when a small area of the die becomes hotter than the adjacent zone, it conducts more drain current, thus creating more heat and pushing the device to failure (thermal runaway), if the appropriate limitations are not set.

Once fixed the thermal coefficient, the device becomes potentially more unstable at high VDS level. The thermal instability condition can be written also as follows (Eq. 4):

(4)

When the VDS voltage increases, the temperature distribution at die level in fact becomes much less uniform, focusing in some small zones of the device. Hot spots determine a localized reduction of the Vth voltage and an increase of the ID current, which generates more heat further reducing the Vth. This condition could cause the thermal runaway and the failure of the device.

Technology Design Optimization
The wide SOA MOSFET technology is the result of a design compromise between RDS(on) and ZTC point. The device shows different areas, having two different gate threshold voltages (Patent proposal 19-CT-0299 registered in USA in Nov. 2020). When the gate-source voltage VGS reaches the first threshold voltage and is lower than the second threshold voltage, the first device portion starts to switch on even while the second device portion is still turned off. In this condition, the overall behaviour of the device substantially coincides with the saturation mode of the first portion, showing a low current value and a good thermal stability.

When the gate-source voltage VGS exceeds the second threshold voltage, both the first and second device portions are active, therefore the total current has a second value equal to the sum of the current of the two portions. In this condition, both portions operate in the ohmic region with a low value of on-resistance RDS(on). Moreover, the high values of the VGS voltage are fixed in order to be higher than the ZTC point of the power MOSFET, which therefore does not present any thermal drift issue.

As a result, the wide SOA MOSFET (Model: STH200N10WF7-2,) offers superior performance compared to an equivalent standard trench device for higher current capability under the same operating conditions, as shown in Fig. 4.


Fig. 4. SOA diagram for the standard trench MOSFET and wide-SOA device.

The standard trench MOSFET is able to withstand a current of 3A at 20V with a 10ms pulse time, while the new wide SOA device can handle a current of 30A at the same conditions. The improved performance is the result of a technology optimization aimed at ensuring quite flat ID current curves at high VDS voltage values.

The main benefit of the technological improvement is the self-limiting current over time, which is crucial for the thermal stability of the MOSFET over a wider range of operating conditions in linear mode. Simulation results show the current stability and transfer characteristics of the wide SOA device compared to the standard trench MOSFET and the best competitor’s device available on the market (Fig. 5).

Fig. 5. Simulated drain current stability over time (on the left) and transfer characteristics (on the right).

As a result of the design trade-off, the wide SOA MOSFET features a low current gain at lower gate-source voltage (VGS), thus limiting the current increase and, consequently, the thermal runaway in linear mode operation; at higher VGS values, the current gain increases, thereby reducing the on-resistance (RDS(on)) under switching conditions. Thanks to this feature, after limiting the inrush current pulse in linear mode at start up, the wide SOA device can also be driven in PWM (Pulse Width Modulation) mode.

Measurement Results
The ruggedness of the wide SOA MOSFET with respect to the standard device was experimentally verified by testing the following condition:

With a fixed ID current of 20A, the pulse duration was increased until the device failure.The measured waveforms just before failure are shown in Fig. 6.


Fig. 6. Measured waveforms for standard trench MOSFET and wide-SOA device at a fixed drain current.

Experimental data highlight the high ruggedness of the wide SOA MOSFET, which survives for 20ms under the stressful linear mode conditions whereas the standard device can only work for 800 µs before failing.

Conclusions
The wide SOA MOSFET exhibits good performance in linear mode working conditions thanks to high ruggedness and thermal stability that prevents thermal runaway. In addition, the new device driven in fully saturation region (linear resistive behavior) is also suitable for switching applications, particularly where the linear mode occurs during the transition phases only. The STH200N10WF7-2 is an ideal choice to design safe and reliable electronics systems.

Further reading

† [1] A. Consoli, F. Gennaro, A. Testa, G. Consentino, F. Frisina, R. Letor and A. Magrì, “Thermal instability of low voltage power MOSFET’s”, IEEE Transaction on Power Electronics, vol. 15, no. 3, May 2000.

† [2] G. Consentino and G. Bazzano, “Investigations on Electro- Instability of Low Voltage Power MOSFETs: Theoretical Models and Experimental comparison results for different structures”, PET 2004 Conference, Chigaco 2004.

† [3] A Raciti, F. Chimento, S. Musumeci, G. Privitera, “A New Thermal Model for Power MOSFET Devices Accounting for the Behavior in Unclamped Inductive Switching”, Special Issue on Reliability Issues in Power Electronics (Si and Wide Band Gap Devices, Interconnections, Passives, Analysis and Applications) on Microelectronics Reliability, ELSEVIER Editor 58 (2016) Conf. Rec. 2019 21st European Conference on Power Electronics and Applications (EPE ‘19 ECCE Europe), 3-5 Sept. 2019, Genova, Italy.


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