The glorious gate oxide
Should one worry about the lifetime of the gate oxide of SiC power
MOSFETs under negative gate stress? Absolutely not, now that experiments
show that they last as long as they do under a positive gate stress.
BY SATYAKI GANGULY, BRETT HULL, DANIEL LICHTENWALNER AND JOHN PALMOUR FROM WOLFSPEED
One of the greatest strengths of the 4H form of SiC is an electric breakdown field that is around ten times that of silicon. This means that for a given voltage rating, SiC power devices can feature a thinner drift region and higher doping than their silicon counterparts. In turn, this allows SiC power devices to have a far lower on-resistance (see Figure 1) and a simple unipolar MOSFET structure – there’s no need for complex architectures, involving super-junctions or bipolar conduction. On top of this, SiC power devices have low leakage currents at relatively high temperatures, and a high thermal conductivity that supports higher current densities, enabled by the low on-resistance.
Figure 1. Unipolar one-dimensional specific semiconductor drift
on-resistance (RON,SP in mΩ-cm2) versus breakdown voltage. Dashed orange
and black lines show the theoretical limits at room temperature (RT)
for silicon and SiC respectively. The RT data points represent various
generations and voltage ratings of Wolfspeed SiC MOSFETs, and the green
dashed line is a guide to the eye for that data. Adapted from J. W.
Palmour et al., Proceedings of the 26th International Symposium on Power
Semiconductor Devices & IC’s, June 15-19, 2014.
Drawing on all these attributes, SiC MOSFETs have demonstrated clear-cut advantages over other material systems, in terms of power density, efficiency, switching speed and thermal management. So significant are these gains that if every data centre on Earth used SiC instead of the incumbent, silicon, Manhattan could be powered for an entire year by the energy savings provided by this wide bandgap material.
The success story of SiC power devices dates back to just after the turn of the millennium. One of the key milestones came in 2002, when our company, Wolfspeed, released its first commercial 600 V junction-barrier Schottky diode. In 2011 we followed this up with the launch of the industry’s first SiC MOSFET, rated at 1200 V; and within a further three years we had introduced the world’s first 1700 V SiC half-bridge module.
More recently we have been grabbing the headlines for our efforts at increasing production capacity. This April we opened the world’s first 200 mm SiC wafer fabrication facility, heralding the electrifying present and future of SiC power devices.
We are not alone in producing SiC power devices, which are finding deployment in automotive, renewable energy, power supply, and industrial applications. Setting us apart from our peers is the broadest commercial portfolio, which currently includes SiC MOSFETs and Schottky diodes in both discrete package and bare die form, as well as power modules. Our SiC MOSFETs scale from 650 V to 1700 V, with on-resistances ranging from 10-1000 mΩ; and our family of Schottky diodes span 600 V to 1700 V, with a best-in-class forward-voltage drop that trims conduction losses and boosts overall system efficiency. We continue to diversify, recently introducing 650 V Schottky diodes in a compact QFN 8 mm by 8 mm package, and 650 V MOSFETs in a TO lead-less package that have a footprint 60 percent smaller than the through-hole packages on the market today. Another breakthrough has been the introduction of our E-Series family of power devices: they are automotive qualified, humidity robust, and optimized for on-board automotive charger, DC/DC converter and drivetrain applications, as well as PV inverters. This launch has further bolstered our reputation for SiC devices in the automotive market space.
Evaluating reliability
SiC power devices offer a level of reliability that is already excellent and on an upward trajectory, thanks to continual advancements in SiC substrate quality, epitaxial growth capabilities and device processing. However, harsh operating conditions, combined with ever demanding and evolving market requirements, are driving gate oxide reliability requirements for SiC power devices ever higher.
There are two key aspects to gate oxide reliability: threshold voltage stability and gate oxide lifetime. Nobel-prize-winning physicist Herbert Kroemer once famously remarked that the ‘Interface is the device’, and rightly so. Owing to differences between SiC and silicon MOS interfaces, SiC gate oxide reliability has always been carefully scrutinized, and judged against the gate oxide reliability of silicon devices.
The threshold voltage stability for the SiC MOSFET is, in general, similar to that for its silicon sibling. However, there are fundamental differences between the two material systems. They include smaller conduction band and valence band offsets between the 4H polytype of SiC and SiO2, compared with silicon and SiO2; the higher interface trap density for the 4H-SiC MOS device; and a difference in the interface chemistry – a nitrided gate oxide is employed for SiC, and hydrogen passivation for the SiO2/silicon interface. Due to all these differences, it is likely that threshold voltage shift mechanisms could differ between SiC and silicon MOS devices.
Within the wide bandgap community, much effort has been devoted to uncovering the mechanisms behind the observed shifts in the threshold voltage of SiC MOSFETs, using bias-temperature instability tests. These investigations have considered both positive and negative gate biases, and demonstrated threshold stability, alongside long-term reliability for practical applications.
The second part of gate oxide reliability, which is gate oxide lifetime, has also been carefully studied for SiC MOS devices. Our company has reported an attractive median time-to-fail gate oxide lifetime of 10,000 years at 175 °C and at a gate oxide electric field of about 4 MV/cm for n-channel SiC power MOSFETs through both constant and ramped positive gate bias time-dependent dielectric breakdown studies.
For silicon MOSFETs, the time-dependent dielectric breakdown is arguably one of the most well characterized and cited failure mechanisms of all time. While several models exist, for SiC the majority of researchers use the linear thermochemical electric field model to explain the time-dependent dielectric breakdown. This tends to provide the most conservative estimation. Of the two more common alternatives, the model that considers the inverse of the electric field gives extremely optimistic intrinsic lifetime extrapolations, so its validity is questionable; and the model based on a power-law governed by voltage is unsuitable, because it’s been developed for ultra-thin gate oxides. Due to these issues, it’s hardly surprising that the linear electric field model is widely used for SiC. This model assumes that a positive gate voltage results in the tunnelling of carriers, which create defects in the oxide film. When these defects reach a critical point, they initiate dielectric breakdown at that local weak point.
Evaluating negative bias
The curious reader may have noticed that while the SiC community’s discussions on the threshold voltage stability encompass both positive and negative gate biases, when it comes to gate oxide lifetime, the focuses is on the positive gate bias stress for n-channel SiC MOSFETs. That limitation occurs because, until our recent efforts, there has been little to no work published on the gate oxide lifetime under negative gate bias for SiC MOSFETs. This is surely a significant omission, given that to turn these enhancement mode n-channel devices off, the channel is shut down by taking the gate bias well below the gate threshold voltage, and at least down to 0 V. From a blocking perspective, devices have no trouble realising this at 0 V gate bias. However, during turn-off, device performance improves by applying a gate bias well below 0 V. Turning MOSFETs off with a negative gate bias trims the turn-off energy loss by increasing the gate current during the turn-off transients – in turn, this forces the gate capacitance to discharge quicker than if turned off using a 0 V bias. Another point to consider is that in systems that employ multiple devices in either a parallel or a bridge configuration, devices tend to be turned off with a negative gate bias. This approach is employed because it provides further protection against parasitic turn-on, which can occur with unbalanced transients across multiple chips in a system. The importance of negative gate bias, and subsequently the necessity of gate oxide lifetime study of SiC power devices under such bias condition, certainly calls for careful investigation thus far overlooked.
To improve the understanding of the gate oxide reliability of SiC MOSFETs under a negative gate bias, we have performed constant voltage time-dependent dielectric breakdown testing on our Gen3 1200 V discrete MOSFETs at 175 °C, with applied negative gate biases much higher than the maximum recommended operating gate voltage of -4 V. Keeping source and drain at ground potential, we evaluated around 30 devices at these three gate stress voltages: -29.5 V, -31 V and -32.5 V. We monitored the gate leakage current of each device individually, which enabled us to collect the individual failure times of the stressed devices during these accelerated tests. For a true comparison, we also performed a positive gate bias time-dependent dielectric breakdown study with gate stress voltages of +29.5 V, +31 V and +32.5 V on Gen3 1200 V devices, using an identical sample size to that of the negative bias case.
We found that the failure times for each of the stress conditions followed a well-behaved Weibull distribution. The extracted value for a characteristic that’s referred to as Weibull β – it’s known as the shape parameter, and it represents failure rate behaviour – is well above 2, indicating an intrinsic wear-out failure mechanism under both positive and negative gate stress. As we found similar failure time distributions and values for Weibull β, we were able to conclude that it is likely that there are similar failure mechanisms under both positive and negative gate biases.
Drawing on the Weibull failure time distribution, the linear electric field acceleration model and the maximum likelihood estimation, we extracted values for the median time to fail and extrapolated the lifetime. We found that the lifetime for the gate oxide is nearly identical for positive and negative bias, with a median time to fail of around 10,000 years (this is for conditions of 175 °C and a gate stress at -15/+15 V, which corresponds to a gate oxide electric field of about 4 MV/cm). We wish to point out that as the recommended negative gate-source voltage of -4 V for a MOSFET to turn-off the channel is generally much lower than the recommended positive gate-source value of +15 V during on-state, the oxide lifetime during the off-state should be much longer than it is during on-state operation (see Figure 2).
Figure 2. Wolfspeed Gen3 MOSFET time-dependent dielectric breakdown
(TDDB) median-time-to-failure (MTTF) versus gate stress voltage at 175
°C. Red data points represent the extracted MTTF values at the gate
stress voltages tested, while solid lines are the fit and extrapolation
as described in the text. Stars represent fiducial points to illustrate
the predicted MTTF lifetime at the recommended operating gate voltage
stress condition (both positive and negative). Adapted from S. Ganguly
et al., IEEE International Reliability Physics Symposium (IRPS), pp.
8B.1-1-8B.1-6, 2022.
At this point, while you may be impressed by the stellar SiC MOSFET gate oxide lifetime under negative gate bias, you might be wondering what is the physical explanation behind this observation. Let us try to explain in a little detail. As we have already mentioned, tunnelling is to blame for the time-dependent dielectric breakdown of the gate, with breakdown occurring once defect accumulation reaches a critical point. It follows that if the levels of current flow under positive and negative gate bias are similar, so will be the extent of damage occurring in the gate oxide, and thus the resulting gate oxide lifetime. This view is credible, given that electrons under positive gate bias see an energy barrier of around 2.8 eV, and holes under negative gate bias see an energy barrier of 2.9 eV. Further support for this view comes from our TCAD simulations and electrical measurements. They show that the similar barrier heights lead to a similar level of Fowler-Nordheim tunnelling current flow under both positive and negative gate biases, thus accounting for the similarity in gate oxide lifetime in the two cases.
We have also established a correlation between the failure locations in a MOSFET unit cell and the failure signatures during time-dependent dielectric breakdown stress. The gate leakage profiles from the time-dependent dielectric breakdown stress under a negative bias show two distinct failure signatures – a soft fail, ‘A’, and a hard fail, ‘B’ – under all three stress voltages (-29.5 V, -31 V, and -32.5 V). We found that the post-failure leakage in type ‘A’ devices is orders of magnitude lower than it is in type ‘B’ failed devices.
As part of this study, we have measured the room-temperature gate leakage current at a range of gate voltages (see Figure 3), for failing devices with differing in-situ leakage signatures. When applying a positive gate voltage sweep, we found that the ‘A’-type and ‘B’-type devices had very similar, high current levels of more than 10 A at gate-source voltage of 15 V. But when we swept with a range of negative gate voltages, results differed markedly. The ‘soft’ fail devices, which we’ve labelled type ‘A’, exhibited a current that’s lower by orders of magnitude than the type-‘B’ devices, which encountered hard failure. This observation is consistent with in-situ data recorded at a higher bias and temperature during the time-dependent dielectric breakdown stress.
Figure 3. Post time-dependent dielectric breakdown negative gate stress
failure, at room-temperature. Typical gate leakage versus gate voltage
current sweep data for devices with two distinct failure signatures
(‘A’: soft fail, ‘B’: hard fail). During positive sweep (VGS > 0)
leakage levels are similar in ‘A’ and ‘B’, whereas during negative sweep
(VGS < 0) the leakage level of ‘B’ is orders of magnitude higher
than ‘A’. Adapted from S. Ganguly et al., IEEE International Reliability
Physics Symposium (IRPS), pp. 8B.1-1-8B.1-6, 2022.
Our next step involved trying to determine whether the different electrical failure signatures – that is, the type ‘A’ and the type ‘B’ devices – have any degree of correlation with the failure locations in a MOSFET unit cell. To see whether this is the case, we undertook physical failure analysis, involving thermal imaging followed by focused ion-beam cross-section and scanning-electron microscopy imaging. These forms of microscopy were performed on multiple failed devices that have the two different failure types.
Inspecting these devices revealed that the subset with a soft fail (‘A’-type) signature had a gate oxide rupture in the JFET gap of the MOSFET (see Figure 4(a)). On the other hand, those with the hard fail (‘B’-type) signature had a gate oxide rupture in the n+/p-well area of the MOSFET (see Figure 4 (b)). This is not just a mere coincidence: it is repeatable across many devices, and it can be explained by considering the energy band diagram of the poly-SiO2-SiC interface.
Figure 4. Schematic cross section as well as focused ion beam,
cross-sectioned scanning electron microscopy images, showing gate oxide
rupture after negative gate bias time-dependent dielectric breakdown
(TDDB): (a) in the JFET gap for the type ‘A’ soft-fail electrical
signature, (b) the n+/p-well for the type ‘B’ hard-fail electrical
signature. Adapted from S. Ganguly et al., IEEE International
Reliability Physics Symposium (IRPS), pp. 8B.1-1-8B.1-6, 2022.
Enthusiastic readers can find a detailed account of our explanation in a paper published earlier this year (for details, see ‘Further Reading’). Here, we offer a simpler alternative. It is our view that during the time-dependent dielectric breakdown stress, if there are gate oxide ruptures in the SiO2, the likelihood is that this will convert the poly-SiO2-SiC interface to essentially a Schottky junction. For the poly-SiO2-SiC that sits over the p-well, the majority-carrier holes will accumulate there under a large negative gate bias. Meanwhile, for the poly-SiO2-SiC over the n+ source, the abundance of the majority-carrier electrons will remain, even under a negative gate bias. It’s a different state of affairs, though, when the rupture takes place in the low-doped n-type SiC JFET gap region. In this case, electrons will deplete under a similar bias condition. This is consistent with our electrical measurements – and offers an explanation of why there is a much higher current under large negative gate bias when the gate oxide breakdown occurs in the n+ or p-well region, than when the rupture occurs in the depleted n-type SiC JFET gap.
For the ruptured areas under positive bias, current flow will always be high under positive bias, because electron accumulation can take place at the n+ source and at the n-type SiC JFET gap region. In the case of failures above the p-well, even though majority carrier holes will be depleted at the p-well and poly(/SiO2) interface under a positive bias, there is still a high current due to inversion electrons in the p-well. So, regardless of whether the gate oxide rupture take place in the n-type JFET, the p-well or n+ area, the resultant gate current level will remain high under positive gate bias.
Our work shows that the gate oxide lifetime extracted from our devices under normal operating and accelerated negative gate bias conditions is a very close match to that extracted from positive gate stresses. This work should help alleviate any concerns regarding the gate oxide lifetime and failure mode under hole transport, rather than conventional electron transport. While our investigation considers a planar MOSFET design, it is possible that similar observations hold for other cell designs, such as those employing a trench. However, experimental verification is required before any claims can be made. Another key finding from our investigations is that the different electrical failure signatures that exist under negative gate time-dependent dielectric breakdown stress correlate with failure locations in a MOSFET unit cell. This observation promises to aid the early phase of any new process development, as it will allow the failure location to be identified from gate leakage data, without the need for physical failure analysis. We hope this insight, as well as others provided by our study, will help the SiC world to power up even more!
Further reading
† A.J. Lelis et al. “Basic Mechanisms of Threshold-Voltage Instability and Implications for Reliability Testing of SiC MOSFETs,” IEEE Trans. Electron Dev. 62 316 (2015)
† D.J. Lichtenwalner et al. “Reliability Studies of SiC Vertical Power MOSFETs,” IEEE International Reliability Physics Symposium (IRPS) 2B.2-1–2B.2-6 (2018)
† J. McPherson et al. “Comparison of E and 1/E TDDB models for SiO2 under long-term/low-field test conditions,” IEDM 171 (1998)
† S. Ganguly et al. 1998 “Negative Gate Bias TDDB evaluation of n-Channel SiC Vertical Power MOSFETs,” IEEE International Reliability Physics Symposium (IRPS) 8B.1-1-8B.1-6 (2022)
