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Cadence GDDR6 IP Is Silicon Proven For TSMC N6 And N7 Process Technologies

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Cadence Design Systems, has announced that Cadence IP for GDDR6 is silicon proven on TSMC's N6, immediately available on both N6 and N7 and forthcoming for TSMC N5 process technologies. The GDDR6 IP consists of Cadence PHY and controller Design IP and Verification IP (VIP) that is targeted at very high-bandwidth memory applications including hyperscale computing, automotive, 5G communications and consumer, with particular relevance to the memory interface in artificial intelligence/machine learning (AI/ML) chips. Using Cadence and TSMC technologies, customers can design chips that connect to GDDR6 memory more quickly and with low risk.

GDDR memories have historically been used in graphics applications, and the DDR and LPDDR memory families have been used for most other types of computing. As we enter a new era of computing that requires even higher memory bandwidth than can be offered by DDR and LPDDR, the industry has turned to GDDR6 DRAM memory to provide the memory bandwidth required to meet the needs of latest generation computing devices.

The Cadence IP for GDDR6 offers more than 2X the data rate of other latest generation standards like DDR5 and LPDDR5, and it requires new architecture and techniques in GDDR6 design IP. Drawing from Cadence's unique experience in both DDR and high-speed signaling, Cadence's PHY IP for GDDR6 allows up to 16Gbit/s bandwidth per pin—512Gbit/s per chip—across the full range of operating conditions, with low operational power and idle power as well as a low bit-error rate (BER) for higher reliability and greater bandwidth. The GDDR6 design can reach even higher speeds in the most advanced TSMC N5 process. The corresponding GDDR6 controller IP provides a strong feature set incorporating performance and reliability features derived from Cadence's DDR controller designs.

“The combination of Cadence's Design IP for GDDR6 and TSMC's N6 process enables silicon designs for AI/ML, hyperscale and other computationally intense applications,” said Suk Lee, senior director of Design Infrastructure Management Division at TSMC. “We look forward to a continued partnership with Cadence to help our customers achieve high performance with design solutions, benefiting from the significant performance and power improvements of TSMC's advanced process technologies.”

“The Cadence Design IP for GDDR6 on TSMC's N6 and N7 processes is immediately available,” said Sanjive Agarwala, corporate vice president, R&D in the IP Group at Cadence. “Our latest PHY and controller Design IP for GDDR6 now provides DRAM data rates at 16Gbps on the TSMC N6 and N7 processes, marking it as the first in the family of devices in advanced TSMC nodes. Additionally, we have taped out GDDR6 on the TSMC N5 process.”

“Micron's GDDR6 memory is rapidly gaining traction beyond graphics and into emerging areas such as AI/ML, networking and professional visualization, all of which demand high-bandwidth solutions,” said Malcolm Humphrey, vice president and general manager of the core compute business for the Compute and Networking Business Unit at Micron. “Together, the Cadence IP featured in the latest TSMC N6 and N7 process technologies and Micron's GDDR6 memory are accelerating the industry's next generation of memory-intensive compute solutions.”

The GDDR6 IP supports the Cadence Intelligent System Design strategy, which enables advanced-node system-on-chip (SoC) design excellence. The IP leverages technology from Cadence's silicon-proven DDR and high-speed SerDes designs as well as comprehensive verification capabilities with Cadence VIP, providing designers with the utmost confidence when implementing SoCs.


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