Advanced Inspection Process Control Increases IGBT Reliability
Integrated power semiconductors constructed on ultra-thin substrates are in high demand, but yield that sacrifices reliability costs manufacturers valuable time and money according to UnitySC's Gilles Fresquet, CEO.
The demand for thin and ultrathin semiconductor devices including power circuits rises continuously, driven in part by explosive growth in high-performance computing, networking, automotive and industrial applications. Quite simply, thinner devices often mean a reduced footprint. But this is not the only benefit. For some applications, and in particular, power semiconductors, the thinner the dies, the better the device performance. Because of this, backside thinning processes are critical manufacturing steps. While macro-inspection is a suitable process-control approach for backside thinning in many applications, full backside wafer inspection is needed for power semiconductors. This is especially true for power devices with backside processing that includes not only thinning, but backside metallization and even backside shallow junction formation. One example is insulated-gate bipolar transistor (IGBT) devices that require final thickness less than 100Âµm. This article examines the importance of full wafer backside inspection for IGBT devices.
The IGBT Story
While not new, the IGBT has become a popular power semiconductor device choice for a wide range of industrial power-conversion applications, due to recent technological advancements such as rugged switching characteristics, low losses and simple gate drives. These applications include strategic emerging and high-growth industries such as high-speed rail transportation, electric and hybrid vehicles, smart grids and renewable energy.
The latest approaches for manufacturing IGBT devices focus on decreasing power losses and switching time. To optimize its performance, the final thickness of a power device is essential. Newer IGBT technology relies on extremely shallow p-doped backside implants to accurately control its emitter efficiency. Any excess in device thickness would result in both an increase of the forward saturation voltage and turn-off losses. Because of this, roadmaps are targeting a final device thickness between 20Âµm and 50Âµm by 2020.
Causes of Backside Defects in IGBTs
For most devices, backside grinding is the most popular method for reducing wafer thickness, due to its relative low cost and high speed. However, the mechanical stress and heat applied during this process can damage wafers. This potential damage needs to be carefully understood and controlled to avoid any negative performance and reliability impacts to the final devices.
An IGBT is a two-layer, bipolar device with a transistor drain that requires not only backside thinning, but also a p and n type backside-doped region formation, followed by metallization to create an active diode. As such, any occurrence of backside defects caused by wafer-thinning processes can be particularly detrimental to the end-device reliability. Compared with standard CMOS, IGBTs can incur defects not only from the thinning itself, but also from the doping process steps that follow.
Ticking Time Bombs
Traditional approaches to backside wafer inspection include manual microscope visual inspection, which is an unrepeatable process that relies on the perceptions of the human eye, with limited defect characteristics. It requires a specific skillset and isn't always fully accurate nor reliable.
Automated optical inspection (AOI) is also used to perform macro-inspection of the wafer surface. Unfortunately, this method, even with increased magnification, is not sufficient for detecting all the defects, particularly those that occur at the nanometer level.
More advanced darkfield inspection might be a solution for some processes. However, due to the high roughness level following the grinding process, the haze level makes the darkfield system almost blind. Additionally, darkfield systems require a perfectly flat surface, and a chucking system is mandatory. For backside inspection, this would mean a chuck on the frontside, which is not possible due to the potential for damage and contamination to the active part of the device.
Nanometer-level defects that go undetected can be ticking time bombs because"”though they will not be discovered during the final probe test for electrical reliability"”they might fail down the road once they are implemented in a system. For example, in IGBT devices, crystal extrusions on a small area of the backside diode can cause it to fail, which in turn creates hotspots in the final device. This device failure could happen at the system level, due to an undetected wafer-level defect. While device failure in a smartphone is a mere inconvenience, in critical applications it can be catastrophic.
Defusing the Time Bomb
To address this growing need for more accurate backside wafer inspection, a new nanometric defect-detection approach has been developed that combines phase-shift deflectometry (PSD) and conformal confocal (CC) inspection technology; Unity's approach is unique and patented.
PSD allows for the detection of topographic wafer defects that are only a few nanometers high, on both the frontside and backside surfaces. Combined with wafer reflectivity and global topography results, PSD provides a reliable method to detect defects such as scratches, cracks, stains and more.
CC technology is based on a white-light beam generated by an LED source that passes through chromatic multi-lenses to separate each wavelength in the vertical direction. It is used to perform wafer-edge inspection (top, top bevel, apex, bottom bevel and bottom) by combining high lateral resolution with a large depth of focus. CC edge inspection detects typical defects, such as chips, shells, cracks, contamination areas and more, which can propagate on the wafer.
Combining PSD and CC into one system for high-volume manufacturing (HVM) provides reliable and accurate surface topography measurement. For example, UnitySC has implemented PSD and CC technology in the Deflector and Edge modules of its 4See Series automated defect inspection platform, so that inspection can be performed all around and through the device wafer (Figure 1).
Figure 1: UnitySC's 4See Series combines PSD and CC technology to perform nanometric wafer backside surface and edge defect inspection after thinning and metallization.
Why Reliability Is More Important Than Yield
Defect detection has always been important during the technology-development phase to adjust processes so that yield is improved. In HVM, finding these defects earlier is becoming more critical to end-device reliability since high yield with low or poor quality is actually a disadvantage for manufacturers. Generating a backside defect map using a system that combines PSD and CC, and then overlaying it with a frontside electrical probe test map allows for a more accurate picture of production yield (Figure 2).
Figure 2a (top) and Figure 2b (right): This backside inspection defect map, shown in the top image (2a), is mirrored and combined with a frontside electrical probe test map in the bottom image (2b), to show all detected defects (red from the backside defect map; orange from the frontside electrical probe map). Every die overlapping a defect is reported as bad if it is determined to be part of the "˜killer' defect class.
At the end of the day, it is important for fab managers, device manufacturers and end users alike to understand that, in critical applications, the reliability of the end device begins at the wafer level. With this understanding and by working to improve reliability, the added value for the fab is that the system integrator will come to rely on them for their high-quality devices, which puts them at a premium.
Device manufacturers are under constant pressure to increase their production yields while also minimizing product defectivity. Both objectives can be achieved by implementing a highly accurate approach to backside inspection with systems that feature nanometric defect-inspection technologies.