GaN power devices: Perfecting the vertical architecture

Optimised trences and tins enable the production of vertical, normally-off GaN power transistors with low epitaxial costs and high blocking voltages By Yuhao Zhang, Min Sun and Tomás Palacios from Massachusetts Institute of Technology

GaN is tipped to revolutionise the power electronics industry. It promises to trim the losses in power conversion circuits, and could drive a 10 percent reduction in global power consumption. What's more, thanks to its capability to handle far higher power densities that today's devices, it could trim the size, weight and cost of power systems.

Initially, the development of GaN power devices focused on a lateral geometry. Recently, however, there has been a growing interest in vertical architectures. Merits of this geometry include: the capability of realising high breakdown voltage and current levels, without having to enlarge chip size; a superior reliability, resulting from the shift in the peak electric field from the surface to the bulk of the device; and a simplification of thermal management, compared with lateral devices. Thanks to these attributes, vertical GaN devices are the most likely contenders to combine currents in excess of 100 A with voltages of more than 600 V "“ the typical requirements for many medium and high power applications, such as electric vehicles and renewable energy processing.

One of the challenges facing vertical GaN power devices "“ like their lateral cousins "“ is the realisation of normally-off operation. That's not the only issue, however: many vertical devices require p-type GaN or epitaxial regrowth. That's not easy, as compared to n-type GaN, the p-type variant has a low ratio for the acceptor activation and a far lower carrier mobility. And if epitaxial regrowth is needed, this greatly increases the complexity and cost of device fabrication.

To overcome these difficulties, our team at the Massachusetts Institute of Technology has developed a novel GaN-based vertical power device that features trench and fin structures, and avoids the growth of p-type material.

Enabling normally-off devices

Trench structures are key building blocks in many modern GaN vertical devices. For example, they have been recently used in trench metal-insulator-semiconductor barrier Schottky rectifiers, where they shield the high electric field at the Schottky contact (see Figure 1 (a)). The addition of the trench greatly enhances the reverse blocking characteristics of the GaN Schottky rectifier by delivering a doubling of the breakdown voltage and a slashing of the leakage current at high reverse biases by a factor of 10⁴.

Figure 1. Trench structures can feature in various vertical GaN power devices, including: (a) metal-insulator-semiconductor barrier Schottky rectifiers, (b) current aperture vertical electron transistors, and (c) MOSFETs.

Normally-off GaN transistors have also benefited from the addition of trenches. They include one of the most widely used vertical transistor architectures, the current-aperture vertical electron transistor. This normally-on device combines the high conductivity of a two-dimensional electron gas channel at the AlGaN/GaN heterojunction with the improved field distribution of a vertical structure. Normally-off operation is possible by switching to a trenched semi-polar gate (see Figure 1(b)).

Another transistor architecture that benefits from the introduction of the trench is the vertical GaN MOSFET. This modification allows it to combine a normally-off operation with a low on-resistance (see Figure 1(c)).

Perfecting trench fabrication

Trench etching and corner rounding are two of the key technologies for making high-quality trenches in high-voltage vertical GaN devices. As the trench corners typically coincide with the location of the peak electric field, and are therefore the most "˜vulnerable' spots for breakdown, their smoothness is highly valued. If there are any rough surfaces or sharp corners in these trenches, electric-field crowding can occur, leading to device preliminary breakdown.

Good results are not possible with the conventional corner rounding process technology that is used for silicon and SiC devices. That's because the high temperatures "“ annealing is undertaken at more than 1000 ËšC "“ deteriorate GaN material quality and device performance.

To prevent this from happening, we have developed a damage-free corner rounding technology for GaN that works at only 85 ËšC. It involves a wet chemical treatment, with a tetra-methyl-ammonium hydroxide etching, followed by a piranha clean. By etching the sidewall along the m-planes and a-planes, the hydroxide eliminates surface damage caused by dry etching, before the etching residues are effectively removed by a piranha clean (see Figure 2 (a), (b) and (c)).

Figure 2 (a)-(c) Cross-sectional scanning electron microscopy images of trench structures right after dry etching, with a following tetra-methyl-ammonium hydroxide wet etching, and an additional piranha clean. (c)-(e) Simulated electric field distribution in the trench-based device unit-cells with three different trench shapes.

We are able to control the shape of the trench by tuning the dry etching conditions and applying the rounding process. We know from TCAD simulation and experimental study that we want to form a flat-bottom rounded trench, because this is the most effective profile for spreading the electric field distribution, and thus provides the best blocking characteristics (see Figure 2(d)-(e)).

Improvement in the blocking capability of trench structures is possible through the addition of advanced structures that shift the peak electric field away from trench corners/bottoms and towards the bulk semiconductor region. Success can result from the incorporation of implanted field rings, or the introduction of carbon-doped GaN/p-GaN hybrid blocking layers near the trench bottoms.

A debut: the vertical GaN fin MOSFET

In trench-based vertical power transistors, the semiconductor regions between the trenches provide the channel for the field-effect transistors. For the current-aperture vertical electron transistor and the MOSFET, realising normally-off operation requires, in the channel region, complicated epitaxial regrowth or p-type GaN layers. Both options are undesirable: the re-growth step significantly increases the cost and complexity of device fabrication; and adding p-type material produces transport properties that are far from ideal, because the mobility of the electrons in the inverted p-type GaN channel is typically at least 50 times lower than that in the n-type GaN regions, leading to high device on-resistance.

Addressing these challenges is our GaN vertical fin MOSFET (see Figure 3). This ground-breaking design consists of only n-type layers of GaN, thereby eliminating the need for material regrowth or p-GaN layers. With this device geometry, current is controlled through narrow, fin-shaped vertical n-type GaN channels that are surrounded by gate metal electrodes.

Figure 3 (a) MIT's novel vertical GaN fin MOSFET architecture. (b) cross-sectional scanning electron microscopy image of a fabricated fin device with a 450 nm channel width.

When our device is held at zero gate bias, electrons in the fin channels are depleted, due to the work function difference between the gate metal and GaN. We select a fin width below 500 nm, because this ensures that the depletion regions induced by the two free surfaces of the fin merge, leading to full depletion of the fin channel and ultimately normally-off transistor operation.

We are able to control the threshold voltage of these transistors by changing the fin width, and we have reported values in excess of 1.5 V. Another attribute of our transistors is the high mobility in the fin channel, thanks to the smooth sidewalls that are produced by the facet-dependent trench formation and corner rounding process.

Following optimisation, our GaN vertical fin MOSFETs produced: an on-resistance of just 0.36 mΩ·cm² for a blocking voltage of 800 V, with forward current in excess of 10⁴ A cm^-2; and a leakage current of only 10^-5 A cm^-2 at a reverse bias of 600-800 V.

More recently we have achieved even better results. Through continuous optimisation of electric field engineering and the fabrication process, we have demonstrated a blocking voltage of 1200 V with an on-resistance of 0.2 mΩ·cm². These results will be published these results will be presented in the 2017 International Electron Devices Meeting (IEDM) this December in San Francisco.

These impressive characteristics show that our design, which incorporates recent innovations on GaN trenches and fins, can pave the way to a new generation of vertical GaN power transistors that feature low epitaxial cost, excellent blocking capability and normally-off operation. That makes these vertical power devices very promising candidates for extending the reach of GaN devices into high-voltage, high-current power electronics.