FEATURE: Finding The Path To Next-gen Chips
New transistor and IC technologies are rising to address the issues of complexity, cost and risk as manufacturers and researchers alike look beyond conventional CMOS device scaling evolution. Multiple manufacturers and researchers are seeking new paths and innovating new processes and materials to find lower cost, higher performing solutions for next-generation chips – We explore several leading and promising avenues for devices below 10nm
Some of the world’s largest semiconductor manufacturers, fabless design houses, startups and materials innovators all share a common goal: create paths to next-generation device technologies that reduce complexity and cost while delivering better performance.
The search for alternatives to existing scaling roadmaps is seen as essential by growing numbers of supply chain industry experts who believe that costs and complexities have grown to the point that only the largest fabs and device makers can compete. While global fab leaders can benefit from multi-billion dollar investments tied to their unique product road maps, opportunities have grown for other technologies; researchers are constantly seeking alternatives and novel approaches that avoid IP and patent issues while offering means to create faster, secure technologies.
Micro electromechanical system (MEMS) sensors exemplify advanced technology untethered to the costs and volumes of 300mm fabs. MEMS designs do not rely on cutting edge hardware, but instead often utilize legacy 200mm technologies including refurbished tools and well established fab techniques. Such fabs can find ample reservoirs of quality, trained operators and service experts anxious to get into a new game.
MEMS technology has amply demonstrated that a major new market does not necessarily require the latest transistor technology wedded to 300mm wafers. The MEMS market took-off with the advent of smartphones in 2007. Today, MEMS growth is pegged as much on new applications including drones and IoT network devices as it is on smartphones. MEMS high-end sensors (HES) support industrial and commercial requirements along with virtual assistants and other end use products that did not exist five years ago. The ideal wafer size for MEMS is presently 200mm, which has led to six new 200mm wafer fabs being built in China to satisfy global capacity requirements.
Many experts see node migrations as moving horizontally or vertically toward 3D designs before large scale adoption of extreme ultraviolet (EUV) lithography that manufacturers such as Intel, Samsung and TSMC have predicted will occur later this decade. Many expect significant improvements at 7nm compared to immediately preceding nodes, which may delay the need for 5nm devices until late in the 2020s. Manufacturers are also expected to create hybrid technologies that incorporate any number of non-traditional approaches including carbon nanowires, fully-depleted silicon on insulator (FDSOI), and different types of wafer bonding. We can expect multiple iterations of existing FinFET and other 10nm architectures before the trek to 7/5nm commences en masse. Meanwhile, the researchers at CEA Leti report that their 3D stacking technology, CoolCube, has reached new performance milestones and that manufacturing partners for pilot production runs are now being sought. The CoolCube approach operates at lower temperatures compared to other bonding techniques, which better preserves transistor functionality during alignment and other processing steps. CoolCube attained offset pitches of 1nm or less in earlier production stages, alignment accuracy that alludes some higher temperature processes.
The drive to find new approaches to device evolution and scaling is also a product of the growing disparity between design and manufacturing capabilities. Traditional node scaling has become so expensive that it is no longer the ‘go-to’ solution for increasing density and performance. To paraphrase the old analogy: if you build it, will the market buy it?
Even the largest companies explore alternatives. This is especially true for fabless design groups that cannot sink billions into each new node since there are not always multimillion device market opportunities to amortize 10-figure investments. While fabless designers explore alternatives, major consumer device manufacturers such as Samsung and Apple are having a go at building their own mobile device chips and major data center operators including Amazon, Facebook and Google are creating cloud chip designs. This shift equates to fewer high-volume markets for independent developers and fewer instances in which high cost designs and fab expenses can be amortized across multi-tier/multi-generational product lifetimes.
Most manufacturers and supply chain vendors wish there was a pipeline full of new end use products like smartphones and laptops just waiting for top-dollar chips in multimillion quantities. There are instead new opportunities requiring a few million devices, or hundreds of thousands of chips to support automotive, Internet of Things (IoT), machine learning, augmented / virtual reality, medical device, wearable and printed flexible circuit applications. Even exciting new markets such as the IoT that is already generating billions in revenue seek low-cost chips, with more than one major potential user of IoT technology seeking advanced devices at less than $1 per chip. Although seemingly ‘chump change’ compared to high price legacy processors, emerging applications including the IoT/IIoT are already driving markets and moved semiconductors to 20 percent growth in 2017.
Once final figures are tallied, it’s expected 2017 sales topped (USD) $400 billion while fab tool sales jumped well beyond $50 billion, both first time milestones. 2017’s growth was uncommon, but the fact that so much ground was gained by emerging applications has prompted market analysts to predict solid opportunities in 2018 and beyond. The SEMI trade group estimates automotive electronics markets (ADAS, vehicle autonomy, infotainment, etc.) will achieve (USD) $280 billion in sales by 2020 and that electronic medical devices will grow to more than $200 million by 2024. Today’s $2 trillion supply chain is projected to reach $4 trillion by 2022. Now that’s potential.
The appetite for alternative technologies is driven by more than cost and complexity avoidance. There is a growing realization that it is simply harder to design, inspect and test devices at advanced nodes compared to 28nm transistors in classic 2D architectures. Physical effects that impact device performance and product lifetime are more fully understood now since industry has tried its hands at next generation ICs. As geometries shrink and die are made from thinned wafers, so also do heat buildup, ESD and signal interference become more critical issues; this often results in more elaborate (and expensive) testing protocols and mitigation techniques. Smaller die also frequently have different current requirements to speed signals across increasingly complex circuit pathways, and even if this is an incremental increase in the microwatt range, it represents still another hurdle that designers and manufacturers must overcome. These factors are of particular concern in the ever-increasing number of mobile applications. An excellent example of new challenges can be found in lithographic edge placement errors (EPEs) that were manageable at larger nodes, but are increasingly counterproductive as geometries shrink to 7/5nm and below.
EUV by itself won’t solve all the issues related to reduced node and transistor feature scaling. Defect elimination also becomes more challenging at the parts-per-trillion scale, which effects multiple critical resources across the supply chain from liquid and gaseous chemicals to filtration, sub-fab vacuum and abatement, and so forth. There is no such thing as a perfectly smooth line at atomic scale and variations that were inconsequential at larger nodes can be ‘killer’ below 10nm.
The issues large and small related to device scaling, increasing performance and reducing power consumption are finding solutions through a diverse array of new tools and materials innovations. In addition, new processes and techniques that improve upon throughput and accuracy of existing techniques are showing promise, not just for emerging markets but also for reducing costs and allowing for more product variation in the multimillion device markets with us today.
Applied Materials, a longtime, industry-leading supplier of materials innovation, is one company that is looking ahead to next-generation needs while it supports current requirements in global high volume manufacturing centers.
At the 2017 SPIE Advanced Lithography conference, Applied Materials’ Uday Mitra, vice president of etch and patterning strategy, coauthored a paper about reducing edge placement errors that reported they had cut the critical line error rate (LRE) from a standard 3.4nm to 1.3nm through the use of the company’s Sym3 reactor and proprietary techniques.
Performance gains can also be achieved through the use of the latest, highly advanced 3D modeling programs such as Coventor’s software solutions that enable designers to perform process integration experiments in virtual space. This data also provides a means to estimate yield losses in pattern transfer due to variations in side wall profiles and LER.
Semiconductor supply chain leaders are also addressing the needs of present and future designers and manufacturers through expansion, diversification and comprehensive services targeting the needs of a more diverse international manufacturing community.
AP&S International GmbH (Donaueschingen, Germany) is a prime example of a company that has reinvented itself, expanded and then redesigned its offerings to meet the needs of global manufacturers. The company specializes in different aspects of wet processing and offers a unique metal lift-off approach to support 3D device manufacturing as well as solutions for both front- and back-end production chains.
To support large companies, research groups and startups—all with unique requirements, the company offers a wide range of tools beginning with manual wet benches through fully automated, multi-chamber systems as both new and refurbished tools. Recognizing that smaller customers often need more assistance incorporating new tools into their operations, the company offers extensive pre-sales and after-sales support, including a fully functioning Demo Center where customers can literally try-it-before-they-buy-it. Support now includes a growing array of IoT interfaces paired with 24/7 off-site customer support that is accessible by technicians whenever needed. At SEMICON Europa (November 2017) the company introduced its augmented reality programs for diagnosis and trouble-shooting. These additional capabilities and a customer service mentality that permeates all they offer is especially beneficial for remedying a wide variety of issues that may arise over the course of production cycles. AP&S also reconditions equipment (their own and other major brands,) which helps startups and research institutes leverage limited capital equipment budgets.
Newer, smaller semiconductors are frequently being designed to utilize ultra-thinned wafers, which present their own unique handling and testing requirements. Defects occurring throughout production, especially during the grinding and polishing (CMP process stages), may crack delicate die or set the stage for eventual device failures.
UnitySC (Grenoble, France) is expanding thanks in part to the popularity of its 4See Series of devices that go beyond traditional backside wafer inspection. Designed to spot nanometer-scale defects, their approach utilizes phase-shift deflectometry (PSD) and conformal confocal (CC) inspection technology; Unity’s system is unique and patented. A number of customers are utilizing the UnitySC system for inspection of two-layer, bipolar IGBT power devices. The company expects greater growth potential as spotting more defects on the backside of a semiconductor as well as its top with one tool becomes more critical with each new device generation.
Another sign of expanding reliance on sophisticated inspection and metrology tools was an announcement by Rudolph Technologies in 2017 that its Firefly inspection system was selling briskly in China and that the first delivered devices had qualified to enter production. Firefly provides high-resolution visual and non-visual inspection to support a variety of advanced packaging processes including fan-out wafer-level packaging, panel- and wafer-level CSP. Rudolph expected over (USD) $5 million in revenue in Q3 2017 from the systems.
As various next-generation device architectures move from design to production, 2017 also experienced growth in areas that are not traditionally seen as the sources of continual innovation: the sub-fab. Reno Sub-Systems (Reno, Nevada, USA) announced that its late-2017 funding round garnered (USD) $11.2 million in investments, which is not record-setting by itself, but interesting in the fact that major backers included Intel Capital, Samsung Venture Investment Corporation, Hitachi HighTech, sk Hynix (a South Korean memory chip powerhouse), Lam Research (that bought advanced modeling expert Coventor in 2017,) and MKS Instruments (USA, with offices across Asia, Europe and North America). Reno specializes in two principal technologies: flow control for gases used in chip making and RF power generation with impedance matching of process electrical loads. Both of the company’s primary products offer substantial increases in performance compared to legacy solutions, and are targeting next-generation device manufacturing requirements where tightly controlled performance and faster production is more critical to a company’s success.
As more semiconductor manufacturers diversify their approach to future markets, this in turn drives responsiveness from vendors who are constantly challenged to develop new ways to address future requirements. One company responding with a growing product line is Brewer Science (USA) that provides materials and processes addressing key device architecture needs by reducing wafer stress, warpage, and high temperature limitations while also enabling faster throughput and reduced form factors.
Brewer Science’s temporary bonding and debonding techniques are especially applicable in fan-out wafer-level packaging (FO-WLP). While the ‘chip-first’ approach has been in high volume manufacturing for some while, the ‘chip-last’ approach is still developing. Brewer sees many of its product solutions as offering a complete range of options for customers, whichever approach they are taking.
Like other companies serving different segments of the supply chain, Brewer Science offers a wide assortment of options to fit the diversity found across global manufacturing. Brewer has supported temporary bonding/debonding requirements across multiple device generations and is one of the few companies to support every major type of physical debonding approach. Their products continue to evolve and now include fourth generation solutions for laser systems; they have succeeded in raising the temperature range of processes they can support up to 350° C.
“We have almost 15 years of experience in temporary bonding materials development and commercialization for the manufacturing of 2.5D, 3D, compound semiconductor, fan-out and other process flows. We realized very early that one product or even one platform of temporary bonding materials may not be suitable for all of the processes used in advanced packaging applications. Each process flow or device type has a unique set of requirements, and we offer a broad portfolio of bonding materials and release layers designed to support these individual processes. This approach results in maximized customer benefits, in terms of delivering simple processes with high yield and low cost of ownership," said Ram Trichur, Director of Wafer Level Packaging Business Development at Brewer Science.
Trichur said that the company is seeing growing interest in the latest generation of tools, especially across Asia and most notably in China. While all customers see benefits, some report rather remarkable results, especially when they had previous solutions that were not delivering as needed.
“All of our customers benefit from the advances (we) deliver, yet some have particularly striking success stories. A manufacturer in North America that was producing compound semiconductor devices and bonding with wax materials had a total yield loss of around 30 percent during backside processing due to the poor thermal and mechanical properties of wax. We introduced a new temporary bonding material, and their yields subsequently increased to over 99%," said Trichur.
In addition to solutions that increase accuracy of mask alignments and that enable processing of thinner films at lower temperatures, manufacturers are also looking to atomic level deposition (ALD) and its cousin, atomic level etch (ALE) to control materials removal much more precisely than in the past. Current etchants are typically used to remove materials across entire wafers, which is not always desirable. ALE offers greater accuracy and continual advancements in the field are redefining precision etching. Applied Materials sees their processes as complimentary with ALE, offering the customer even more control including a new approach under study that would enable the ability to ‘erase’ unwanted material without substantially delaying production, implementing EUV, or installing other leading-edge lithographic tools.
Directed Self Assembly (DSA) continues to gain interest as a means of supporting advanced node scaling while it also helps reduce line-edge roughness (LER). Brewer Science joined with Arkema Group in 2015 to facilitate high-volume production of first-generation DSA polymers. Arkema is a high performance materials specialist based in France with a global presence and 2016 sales of 7.5 billion euro.
Brewer Science also is developing second-generation polymers that are essential to enabling DSA at future nodes. The partnership between Brewer and Arkema now seeks to commercialize these high-x (chi) block copolymers for DSA. First generation polymers supported devices down to 22nm while generation two research targets 5nm and below, which the company and most industry experts agree is critical to extending device scaling without relying on EUV or complex multi-patterning schemes.
“DSA represents a lower cost and higher throughput solution over EUV, but another big cost advantage lies in the reduced mask requirements. DSA still needs lithography and etch processes, but these are lower cost compared to multiple patterning. EUV masks are a significant part of the EUV step cost. DSA also offers a technical advantage that it can reach lower feature sizes now than other patterning technologies," said Hao Xu, Director of Semiconductor Business Development at Brewer Science.
In addition to its cost advantages over EUV, Brewer indicated that it continues to explore DSA advantages because they see the process as complimentary with EUV. Companies that have already committed to EUV may conclude that combining DSA with EUV will better support their goals.
“DSA and EUV are complementary because smaller pitches can be printed with EUV that are not accessible with immersion litho. Smaller pitches means two things: lower multiplication factors can be done with DSA, which leads into lower possibility for defects. Also, there is the possibility of eliminating the trim etch step in the chemoepitaxy flow when using EUV. EUV can also provide graphoexpitaxy templates for contact hole multiplication. It is also important to note that because of the resolution limitations of EUV at smaller nodes, it is possible that DSA will help stretch out the timing for, or even eliminate, the need for high-NA (numerical aperture) EUV tools," Xu added.
EMD Performance Materials (a division of Merck KGaA, Darmstadt, Germany,) continues to grow its commitment to advanced semiconductor processing materials science. Rico Wiedenbruch, head of the IC Materials Business Unit at Merck, said his unit is focused on the many scaling related challenges that the industry faces, offering a wide variety of novel solutions to meet these demands and solve miniaturization roadblocks that challenge the limits of physics. The company’s advanced precursors for atomic-layer deposition are a turnkey solution for producing very thin, highly controlled conformal films, he indicated.
The EMP portfolio extends to a number of areas for conventional semiconductor manufacturing including front- and back-end packaging. Wiedenbruch noted that EMP’s latest solutions target microprocessors, DRAM and NAND Flash memory and are being extended to support ALD precursors for memory devices and 3D NAND cells. He noted some of the biggest problems customers face have to do with pattern collapse, which they address with their FIRM line of processing rinse materials; they also offer block copolymers for DSA. Their line of RELACS Shrink Materials are designed to support the manufacture of devices with much more narrow features than was previously possible.
While materials suppliers are developing and proving resources for next-generation nodes, others are utilizing those tools to further advance such technologies as 3D stacking. CEA Leti (Grenoble) and EV Group (St. Florian, Austria), announced late in 2017 that they had achieved what both organizations believe is an industry first: a successful 300mm wafer-to-wafer direct hybrid bond with pitch dimension connections as small as 1µm (micron).
Vertical stacking of semiconductor devices has become an increasingly viable approach to enable continual progress towards greater device density and higher performance. Wafer-to-wafer bonding is an essential process step in building 3D stacked devices. Tight alignment and overlay accuracy between the wafers is required to achieve good electrical contacts while minimizing the interconnect area at the bond interface. This is a critical factor since achieving it increases space for more viable die on each wafer, thus delivering higher yield. The constant reduction in pitches that are needed to support component roadmaps is fueling tighter wafer-to-wafer bonding specifications with each new product generation.
The product demonstration at Leti’s facilities in Grenoble utilized an EV Group Gemini FB XT automated production fusion bonding system.
“To our knowledge, this is the first reported demonstration of sub-1.5µm pitch copper hybrid bonding feasibility," said Frank Fournel, head of bonding process engineering at Leti. “This latest demonstration represents a real breakthrough and important step forward in enabling the achievement and eventual commercialization of high-density 3D chip stacking."
Research into alternative approaches to transistor design and manufacturing is a robust activity at Leti, the imec group (Leuven, Belgium,) and multiple Fraunhofer institutes in Germany and elsewhere. One recent announcement from imec researchers involved gate-all-around nanowire field effect transistors (FETs) that they organized into a novel vertical configuration. This technology is considered a strong candidate to extend today’s CMOS scaling to its ultimate limit. With an excellent performance-to-area ratio, vertical nanowires seem particularly attractive for making highly dense static random access memory (SRAM) cells, imec notes. Moreover, when used to build those SRAM cells, vertical nanowire FETs may play a key role in hybrid scaling – an emerging approach that integrates multiple transistor architectures in one system-on-chip.
Nanowire FETs can be implemented in a lateral or a vertical configuration. Devices configured laterally still utilize conventional 2D layouts, which means they will eventually hit physical limits that are similar to the roadblocks that existing FinFETs are already experiencing. In the case of nanowires organized horizontally, the space available for gate and contact placement will become so small that the devices may no longer function effectively. Moreover, in the back-end-of-line, too many metal lines in increasingly narrow spaces can give rise to interconnect routing congestion and the possibility of current leakage. Imec researchers believe these issues present an opportunity for vertical GAA nanowire FETs. With these devices, designs can move from 2D to 3D layouts, wherein the gate length is defined vertically. Such a disruptive innovation requires early process-design co-optimization, but it also means that the gate length can be more relaxed without consuming a larger area on the wafer. It also allows some relaxation in the nanowire diameter while preserving control over the short channel effects.
Traditional CMOS scaling has become increasingly complex and expensive, which has led semiconductor manufacturers to seek alternatives to meet demands for higher performance at lower costs. That drive includes the development of extreme ultraviolet (EUV) lithography to replace multi-patterning immersion litho; the latest EUV forecasts by ASML (The Netherlands) and mega-scale manufacturers Intel and Samsung indicate EUV is reaching stabilization. Once implemented, EUV is likely to require additional refinement to extend the number of wafers per hour that can be produced with acceptable yields. Intel, Samsung and TSMC have all indicated they plan to utilize EUV at future technology nodes, varying between 7nm and 5nm. At the same time, all major manufacturers are seeking alternatives for long-term device scaling that either avoids EUV altogether or delays its introduction.
Scaling (with or without EUV,) below 5nm is possible. An increasing number of researchers, device manufacturers and materials experts are exploring alternatives to the ‘brute force’ scaling approach that previously served industry when moving to a new node meant a relatively simple exercise in miniaturization. The future of transistor design for high performance requirements will no doubt include a variety of approaches that could feature various 3D architectures using bonded and stacked devices, and alternative technologies such as fully depleted silicon on insulator (FD-SOI) championed by Globalfoundries, STMicroelectronics, CEA Leti and Samsung, among many companies. Atomic scale deposition and etch will likely support these strategies as materials science continues to play a larger role supporting new architectures and processing techniques.
Multiple strategies are certain to emerge as effective means for enhancing performance while controlling costs within the global semiconductor marketplace. While major consumer product segments including smartphones, computing and entertainment are expected to continue driving memory and other high-performance applications at high volume, more opportunities are emerging that will require lower volume approaches and rapid customization. Emerging applications such as the IoT, the IIoT, automotive electronics, medical and wearable electronics are shaping a new global semiconductor market and will continue to do so in the years to come.