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Intel patent application describes deep gate device with group III-V or germanium active layers

Design targets junction leakage suppression 

The US Patent and Trademark Office (USPTO) has published a patent application filed by Intel process engineers describing a deep gate semiconductor device that uses either germanium or group III-V active layers. The idea is to reduce parasitic leakage current in small feature-size devices.

Shrinking transistor size allows more functions on a chip but it presents increasing difficulties -  in particular the growing need to optimise the performance of each transistor to reduce leakage current and power consumption. 

Multi-gate devices, such as tri-gate transistors, have become one answer. In a tri-gate, by stacking a single gate on two vertical ones, there is more surface area for electrons to travel. 

In conventional processes, tri-gate transistors are generally made on bulk silicon or silicon-on-insulator substrates, which offer reduced leakage. Bulk silicon substrates are preferred as they are cheaper and  tri-gate fabrication is easier,  but it is often difficult to align the base of the metal gate electrode with the source and drain extension tips at the bottom of the transistor body. 

Proper alignment is needed for optimal gate control and to reduce short-channel effects: if the source and drain extension tips are deeper than the gate electrode, punch-through may occur; alternately, if the gate electrode is deeper than the source and drain extension tips, the result may be an unwanted gate capacitance parasitics.

Deep gate all-around

Intel's patent application describes a solution in the form of a deep gate-all-around device, which it says is particularly suited for germanium or III-V material-based FETs with nanowire or nanoribbon channels. III-V materials are receiving a deal of interest as possible channel materials for future mainstream logic chips due to their high bulk electron mobility, which can improve the power /performance tradeoff. 

Gate-all-around transistors are similar to FinFETs and Omega-FETs, which have their conducting channel wrapped with silicon, which forms the body of the device. The thickness of the silicon 'wrapper' determines the channel length. The method provides better electrical control over the channel and helps reduce leakage current. A gate-all-around differs from in that the gate material surrounds the channel region on all sides.

The device described in the patent application and illustrated above comprises: a buffer layer on a substrate; an active layer on the buffer layer; a gate electrode stack on and completely surrounding a channel region of the active layer, and also within a trench in the buffer layer; and source and drain regions positioned in the active layer and in the buffer layer either side of the gate electrode stack. The gate electrode stack is located to a depth in the buffer layer sufficiently below the source and drain regions to block a substantial portion of leakage from the source region to the drain region.

The full details are described in US Patent Application 20140203327.


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