Perfecting GaN Power Electronics With Vertical Devices

A vertical architecture holds the key to producing rugged transistors with a small footprint and a very high operating voltage

IT IS HARD TO IMAGINE a world without electricity. It is this form of energy that powers so much of what we own and use, from PCs and TVs to clocks, light bulbs and the internet.

In different situations, we require different forms of electricity. Consequently, there is a need for an interface, based on power electronics that manipulates the frequency, amplitude and the phase of the electrical source. Conversion of electricity in this manner takes place in: laptop chargers, which convert AC power coming from the socket at between 110 V and 260 V, depending on the country, to 19 V DC power; in solar inverters that must transform 48 V DC power to 220 V AC power; and in an electrical vehicle, where a 200 V DC battery is used to drive a 650 V a three-phase AC motor.

At the heart of all these power systems are semiconductor devices, gate drivers and controller circuits. All these elements currently employ silicon devices − a combination of Schottky diodes and p-i-n diodes, and classes of transistor such as the MOSFET and IGBT 

Thanks to advances in the performance and the reliability of silicon-based power devices, voltage-manipulating electrical systems are more efficient, lighter and smaller than their predecessors. But this trend cannot continue throughout this decade and beyond, because the performances of silicon devices are encroaching their fundamental limits.

By far the best way to overcome this limitation is to turn to a new breed of semiconductor device, made from wide bandgap materials. Armed with SiC and GaN devices, electrical systems can be far lighter, smaller and more efficient than they are today. 

Many firms are already working with wide bandgap materials, with the aim of either breaking into or expanding their share of the multi-billion dollar power semiconductor device market. This includes our team at Avogy of San Jose, California. Founded five years ago, we are pioneering the production of vertical GaN devices that are made on native substrates. Attributes of these novel, MOCVD-grown devices − which features current flow perpendicular to the wafer surface, and a drain contact on the backside of the substrate − include an incredibly low reverse-leakage current and a tremendous reliability at high temperatures. 

By controlling doping in the drift layers, we can realise vertical architectures with drift layer thicknesses of 6 mm to 40 µm and a net carrier electron concentration as low as 1 x 1015 cm-3. These characteristics enable the production of devices spanning a wide range of breakdown voltages.

Why GaN?

We make our devices from GaN because this material’s properties are better than those of SiC, and are vastly superior to those of silicon. Strengths of GaN and its related alloys include: high bandgap energies, which are responsible for low intrinsic carrier concentrations that aid high-temperature operation; attractive transport properties, such as a high electron mobility and a high saturation velocity; a high critical breakdown electric field; and a high thermal conductivity. 

A meaningful benchmarking of power devices must combine an assessment of the performance of blocking and conducting modes. A highly capable device must marry a low resistance, described by its specific resistance (Rsp), with a high blocking voltage that will enable it to sport a high breakdown voltage. These conflicting requirements for a unipolar power device have been captured by a figure of merit that is governed by the square of the blocking voltage, divided by the specific on resistance − this is roughly equal to the product of electron mobility and the cube of the critical electric field at which breakdown occurs (see Figure 1). 

Figure 1. Power device figure-of-merit comparison of wide bandgap semiconductors.

It is the cubic dependence on the critical electric field that enables wide bandgap devices to be vastly superior to those made from silicon. The critical electric field for silicon is 0.3 MV/cm, while it is at least 3.5 MV/cm for bulk GaN, and it could be as high as 3.75 MV/cm. Due to this order-of-magnitude supremacy in the critical electric field, if we ignore thermal and self-heating effects, we can expect a vertical GaN device to exhibit the same breakdown voltage and on-state resistance as a silicon equivalent, while having a footprint that is a thousandth of the size.

In practice, the shrinking of the footprint may not be quite as substantial as this − but it still delivers massive benefits. Smaller devices have lower capacitances, and they can switch at far higher frequencies, which allows a trimming of the size of the energy storage elements, a combination of inductors and capacitors. 

Figure 2. Cross-sectional, scanning-electron microscopy image of Avogy’s vertical transistor. In this device architecture current flow (yellow arrows) is from source through the channel and down the aperture to the drift region. Current flow is controlled by both the top and buried p-GaN gates.

The flaw in lateral thinking

For power applications, it is common knowledge that lateral devices are inferior to their vertical cousins. The vertical architecture −a HEMT in the case of GaN − is better suited to realizing higher breakdown voltages, thanks to the opportunity to deposit an arbitrarily thick electron drift layer. What’s more, vertical devices can deliver higher currents, such as 50 A or more, without the need for a parallel architecture; they are less prone to thermal management issues, thanks to power dissipation in the bulk volume; and the die-yield-per-wafer is higher, because electron drift regions extend into the device, rather than spread out laterally. 

It is worth noting that vertical devices are actually the norm in power applications − this is the architecture of silicon and SiC devices that are operating above 600 V. Taking this route with GaN raises a question regarding the choice of substrate. It is possible to grow GaN layers on foreign substrates, such as silicon and SiC, but thermal and lattice mismatches with GaN make it very challenging to realise electron-drift regions with a thickness of 10 µm and a high material quality. If these layers are too thin, the breakdown voltage is compromised; and if the epilayers have a defect density in excess of 108 cm-2,  this impairs both yield and critical characteristics, such as  breakdown voltage, off-state leakage current and reliability. The latter includes the operating life of the device, its high-temperature reverse-bias behaviour and avalanche ruggedness.

Despite the many compelling reasons for using native substrates for fabricating vertical GaN power devices, there are very few reports by teams pursuing this approach, due to the lack of availability of low-defect-density (less than 106 cm-3) bulk GaN substrates. Compounding this, it is often assumed that bulk GaN substrates are too expensive to be commercially viable. That’s not actually the case, however. Today there are many suppliers of bulk GaN substrates, and due to research and development efforts, material quality is improving rapidly. High prices, meanwhile, are becoming less of an issue, as they fall through economies of scale, thanks to increasing use in the optoelectronic industry. It is also important to note that vertical devices that are fabricated on native substrates have a far smaller die area than lateral structures, and they can expand the breakdown-voltage-limited, safe-operating-area to well beyond 600 V.

Figure 3. Zolt Plus: Just one device is needed to charge laptops, tablets and phones simultaneously

We are highlighting the high voltage capability of these devices by producing GaN diodes with breakdown voltages of 4000 V. Reduce this to 1200 V, and we are able to routinely reach pulsed current levels of 400 A. We are investigating the capability of devices operating with this breakdown voltage within the ARPA-E funded SWITCHES programme, where we are targeting cost parity with silicon equivalents. If we fulfil this goal, our GaN devices will be very competitive, thanks to a switching speed that is superior to that of the incumbent device by a factor of 10 to 50.

One necessity for vertical devices − but not for their lateral peers − is that the device is properly terminated around the edges, while electric field gradients are accommodated within the structure. We have succeeded in this endeavour by modifying junction termination extension strategies originally developed for vertical silicon and SiC devices. Efforts were also directed at the development of robust ohmic contacts for p-type GaN, as well as a bottom n-type contact that is formed on nitrogen-rich GaN.

We have evaluated our wide portfolio of vertical field-effect transistors, extracting values for various material characteristics, including electron mobility, minority carrier lifetime and thermal conductivity. We have plugged these values into sophisticated device models, and by accounting for thermal (Joule) heating effects, we have been able to develop scaling rules for our vertical devices. This has given us a toolkit for determining the size of devices and generating cost models. Additional support for developing vertical-junction, field-effect transistors has come from the knowledge acquired from studying p-n devices.

Today, we are in pre-production with a structure that is flexible enough to accommodate normally-on and normally-off implementations (see Figure 2). We are pursuing the normally-on variant, because it is a more manufacturable device. Due to the lack of a mature, viable p-type ion implantation and activation scheme for GaN, we have developed planar, selective epitaxial MOCVD growth techniques for defining the n-GaN channel regions and the top p-GaN gate regions. These are added after etching an aperture in the buried p-GaN layer.

With our devices, the buried p-GaN region must be connected to the source (in the case of normally-off devices) or to the gate (in normally-on devices), rather than left floating. We have also developed a plug process, so that we can form an ohmic contact on an etched p-GaN surface. 

This approach, which is protected by more than 60 patents, has enabled us to demonstrate field-effect transistors with breakdown voltages exceeding 1500 V and forward currents of more than 5 A. As expected, the vertical architecture of these transistors enables them to be free from threshold voltage shifts, on-resistance degradation or collapse, and reductions in drain current collapse during operation or under high temperatures stress. With breakdown voltages of up to 4 kV, and drive current capabilities of up to 400 A, our devices can target myriad markets (see Table 1 for a listing of regular market segments, and the incumbent semiconductor technologies serving these applications). Out of all these opportunities, we have started by targeting the power supply market. This is being pursued through our Zolt brand, a range of the world’s lightest, smallest and most efficient laptop chargers (see Figure 3). At the heart of these products is our proprietary and patented core systems (resonant switching topology) and component technologies.

Our company’s next steps include working with bulk GaN substrate vendors to: further improve substrate quality; cut the cost of bulk GaN wafers; and quickly see the launch of 4-inch substrates. Device-related efforts will include developing higher current capability, designing higher-power electronic systems for data centres and solar applications, and conducting further reliability studies that should prove that vertical transistors formed on native substrates fulfil standards required by automotive markets.

Table I. Power electronics market segments and semiconductor technologies.

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