As more and more power semiconductors reach mass production, can test systems take the strain, asks Compound Semiconductor.
Reedholm Instruments' latest wafer-level DC test system is set to expose defective power devices.
Earlier this year, US-based test and measurement manufacturer, Reedholm Instruments, unveiled DC test system to characterise power devices at the wafer level.
Based on a modern parametric tester, the instrument promises precise and fast device measurements that quickly weed out defective devices prior to packaging.
Earlier this year, US-based test and measurement manufacturer, Reedholm Instruments, unveiled a DC test system to characterise power devices at the wafer level.
What's more it can handle handle voltages up to a hefty 10 kV, at a compliance current of 10 mA, and currents of 50A. And high current can be reversed to make body diode measurements to 50A without second pass measurements.
For Joe Reedholm, president of Reedholm Instruments, testing high power semiconductors is a 'continuum' of silicon device testing that demands the same parametric tester but with a difference.
As he highlights, these devices are used in extreme conditions and have to switch a great deal of power.
High voltage testing at the wafer level demands a properly designed safety system, with for example, interlock mechanisms between the prober and instrument, to protect the user from these voltages.
But to date, manufacturers of high power semiconductors have largely relied on commercial instruments, used to test silicon devices, reconfiguring these for GaN or SiC testing.
For example, several instruments are often combined to extend the range of a single instrument.
"It's really difficult when you are inventing something to specify your test system so of course the engineer starts testing and adding pieces to a collection," says Reedholm. "So a lot of test systems wind up being put together like laboratory systems yet many engineers just don't have the experience to deal with [the challenges] of high power testing."
As he points out, devices can rupture while under test, generating a very large radiated energy field.
"This gets into the electronics of the test system, disrupting programming and instrumentation, a lot of which is now microprocessor based," he says. "It can also get through the wiring into the test probe, causing the prober to lose control and it's not necessarily easy to deal with that."
And as more and more GaN and SiC devices head for commercial production, safe and efficient testing is only going to get more and more critical.
"[Engineers] end up with something that may be functional but can't be replicated easily or brought under control once you need high volumes of test data," points out Reedholm. "And we're now finding that they need high enough volumes of data to sample and prove to potential customers that they have a robust process that can deliver the product when its needed."
Ready for action
But are today's test instruments ready for high power semiconductors? Reedholm thinks so.
For starters, he highlights how his company's latest 10kV/50A DC power parametric analyser contains software to enable precise measurements at production speeds.
"No compiling is needed... to perform complex calculations," he says. "Engineers don't have the time to amend tests as they go, so this system has a toolset to do that; you literally just fill in cells for testing."
Meanwhile, he is adamant the equipment is coping with rising market demands. As he points out, the rise of SiC and GaN semiconductors has been relatively slow, giving, for example, manufacturers of test interface equipment enough time to modify the latest test probes for high voltage and high current testing.
"Given the demand for, say, solar power inverters, it's inevitable there is going to be a need for these high power devices," says Reedholm. "But while we see the demand for SiC and GaN increasing, it hasn't exploded in the way it was forecast to."
And while the market really gets going, suppliers of parts for test equipment are developing innovative ways to handle higher currents and voltages.
As Reedholm highlights, Austria-based T.I.P.S, for one, has developed probe cards for testing power semiconductors, at a wafer level, under a protective atmosphere.
Here, the wafer area under test is covered with a pressure chamber and flooded with gas to avoid high voltage flashovers. What's more probecards can now be used to protect probe tips and bond pads beneath and around contacts from thermal damage due to current overload.
But why not simply skip wafer-level testing and test the packaged device? Indeed, much development is also underway to test the many different packages of high power semiconductors.
Reedholm admits this is an option saying: "Wafer-level testing can be a science-based art... and you could just say I'm not going to worry about the wafer, package everything and then live with the waste of packaging defective devices."
But as he adds: "Wafer-level test instruments can eliminate defective devices and we have the high speed tests to do just that."