Larger Wafers Slash GaN MMIC Costs

High-quality wafers processed on a 150 mm GaAs fabrication line promise lower GaN MMIC production costs 


RF and microwave power amplification is undergoing a revolution, thanks to the development of the GaN HEMT. By switching from the previous incumbent material, GaAs, to the wide bandgap alternative, GaN, it is possible to achieve the same electron mobility and high frequency response as GaAs with an order of magnitude hike in RF power density, which stems from a five-fold increase in breakdown voltage and a doubling of drain current. Consequently, when GaN HEMTs are constructed with today’s industry-standard processes and sport gate lengths ranging from 0.15 mm to 0.5 mm, they can deliver wide bandwidth, high power and high efficiency at frequencies ranging from 0.1 GHz to 100 GHz.

To exploit these demonstrated performance advantages in commercial and military systems, many groups from around the world have turned their attention to improving the affordability of this GaN transistor technology. To drive down costs, they are scrutinizing several factors: the price of materials, which includes starting wafers, metals and chemicals; labour; process yield; and process uniformity.

Properly evaluating the cost of new technologies is not trivial, and it is possible to compare the affordability of GaN MMICs in different ways. Judged in terms of a key metric – dollars per watt of RF output power – GaN HEMTs produced on 100 mm SiC substrates already undercut their GaAs cousins formed on 100 mm and 150 mm wafers. However, superiority on that front is often outweighed by the comparatively higher price of individual GaN chips, and this higher outlay is still seen by many as an impediment to far greater deployment of this class of device.

One approach to increasing sales of GaN MMICs is to take the well-trodden path for trimming production costs employed within the semiconductor industry. This involves introducing larger wafers, exploiting the economies of scale afforded by batch processing. In the high-volume silicon fabs, ICs are now produced on 300 mm wafers, and migration to a 450 mm platform is under consideration. Similarly, GaN-on-SiC migrated from 50 mm wafers to 75 mm and 100 mm variants over the past decade, with material suppliers II-VI and IQE having recently gone even further – in 2013, IQE unveiled 150 mm GaN-on-SiC epiwafers based on advances in SiC substrates and epitaxial growth.

Yield must not be compromised, however, if the introduction of larger wafers is to lead to substantial cost saving – and history attests that accomplishing this feat can be quite challenging. In the 1980s, when MESFET makers transitioned to larger wafers, there was initially a drastic falloff in yield. Primary reasons for this were a lack of control and non-uniformity in gate recess depth that resulted from a process based on time-of-flight wet etching (later, this weakness was mitigated by the introduction of spray etchers).

Note, however, that migration to larger wafers does not necessarily have to cause yield to nosedive. In the 1990s, MMIC foundries were able to cleverly combat yield loss when scaling pHEMTs by adding etch-stop layers to the epitaxial structure and employing selective recess etching. With these process refinements, engineers realised excellent gate recess etch uniformity, limited primarily by starting wafer uniformity.

Our team at BAE Systems has enjoyed a similar experience as we have scaled our GaN-on-SiC HEMT process to make it suitable for 150 mm wafers. One of the merits of many GaN-on-SiC HEMT processes, including our own, is that they require no gate recessing. Consequently, device and circuit uniformity is highly dependent on epilayer uniformity – and if the starting wafer is uniform, GaN devices, if fabricated carefully, can be nearly as uniform.

We have calculated that per-chip fabrication costs can plummet by 50 percent when the GaN-on-SiC process is migrated from 100 mm to 150 mm wafers (see table 1). Note that this analysis does not include the additional cost of back-end steps, such as on-wafer test, wafer dicing and chip inspection. These post-processing steps become somewhat more efficient with larger wafers, but the gain is not nearly as high as the two-fold improvement associated with fabrication. This is a drag on the overall reduction in chip cost, which in practice is typically 40 percent.


Table 1: Relative cost of 150 mm versus 100 mm GaN-on-SiC processes, normalized to 100 mm. Usable wafer area subtracts a 5 mm unusable epi/process ring along the outer edge of each wafer, and cost per good chip assumes yield is maintained at the same level as wafer size is increased.

In our case, the benefits of switching GaN-on-SiC MMIC production to a 150 mm line are more than just a trimming of chip fabrication costs due to scaling. Visual and line yields are also higher, thanks to increased automation, and fewer wafers are required to meet customer delivery quantities, lowering cost associated with wafer qualification. What’s more, because we have been running 150 mm GaAs processes (MESFET and PHEMT) in our facility for more than a decade, we are able to draw on a great deal of relevant expertise. This has helped us to demonstrate the industry’s first 0.2 mm GaN MMIC process on 150 mm SiC substrates (see Figure 1).


Figure 1: A fully processed 150 mm GaN HEMT MMIC wafer.

Other firms are moving in a similar direction, with plans to release processes on wafers of this size – for example, RFMD announced that in 2014 it will release a process with a 0.5 mm gate length that is targeted at low frequency commercial applications. In comparison, the gate length for our processes is just 0.2 mm, so our MMICs are widely applicable for defence applications at frequencies up to around 50 GHz.

Choosing the right material

Production of all of today’s GaN RF devices and MMICs is undertaken on one of two competing material systems – GaN is deposited on substrates made from either silicon or SiC. When grown on the former, there is a potential cost advantage, in part due to the ability to scale to larger wafers, such as those with 200 mm diameters. However, this advantage has to be weighed against the inferior thermal conductivity and electrical resistivity of the silicon substrate, which compromises both the high frequency and power performance of devices and circuits fabricated on this foundation.

For high-reliability military applications, this compromise is generally unacceptable, making GaN-on-SiC the preferred technology. Devices made with this combination of wide bandgap materials feature an intrinsically higher thermal conductivity for the substrate that results in lower channel temperature, which improves both the performance and long-term reliability of GaN power amplifiers produced in the process.

The epiwafers that we process on our 150 mm line feature an AlGaN/GaN structure with a thin GaN cap and an iron-doped GaN buffer. This particular heterostructure provides a high sheet-charge density for high full-channel current and output power while maintaining good reliability.

Our starting material is provided by epiwafer manufacturer IQE. Growth of the nitride epilayers takes place on the 4H polytype of SiC that is loaded into a state-of-the-art multi-wafer production MOCVD reactor, which is capable of delivering improved uniformity over larger wafer areas. Wafers exhibit a low density of defects, with the majority being substrate-related micropipes and polytypes. Sheet resistance uniformity is 1.2 percent, which is slightly better than that for theheterostructures grown on 100 mm predecessors; and compositional uniformity is excellent, with variations in aluminium content of below 1 percent.

One of the challenges associated with hetero-epitaxial growth is the warping and bowing of epiwafers, which stems from differences in lattice constant and thermal expansion coefficient between the epitaxial layers and the substrate. In the worst cases, epiwafers can even crack. However, even deviating from being perfectly flat by a fraction of a millimetre can render wafers unsuitable for processing.

Our 150 mm GaN-on-SiC epiwafers are formed on substrates that are 500 mm thick. This is similar to the thickness of the substrates used for the 100 mm GaN-on-SiC process, and the reduction in thickness-to-diameter ratio associated with scaling has meant that it was initially a challenge to realise an acceptable warp.

To address this, engineers at IQE performed a series of experiments, and used their findings to refine their processes so that bow and warp for the 150 mm epiwafers could be reduced from in excess of 100 mm to typically 40 mm. This level of warp is suitable for high-yield wafer processing.

Processing and performance

Automated cassette-to-cassette equipment is employed in our 150 mm line, leading to reduced manual wafer handling and increased yield. With this tool-set, our development of a process for 0.2 mm GaN-on-SiC MMIC fabrication has been quite straightforward – the bulk of the effort went into optimizing the existing 100 mm GaN mesa, ohmic, nitride deposition and via-hole formation processes using 150 mm tools to achieve good uniformity and yield on the wafers (see Figure 2 for a scanning electron microscopy image of a representative GaN HEMT device, where the 0.2 mm gates and field plates are patterned using electron beam lithography).


Figure 2: 0.2 mm gate-length field-plate GaN HEMT device.

We have also developed a 150 mm backside process. Although some of the process steps and tools required for this – such as the SiC grinding machine – have taken time to establish, we have not noted any backside process-related issues. Thickness uniformities of less than 5 percent are possible across wafers with a final thickness of 100 mm (see Figure 3 for an example of fully plated-through via holes produced as part of this backside process).


Figure 3: Scanning electron microscopy image of fully plated-through 60 mm square vias.

To test the capability of devices produced on 150 mm wafers, we subjected these transistors to a series of DC and RF tests, comparing their performance to those fabricated on the 100 mm line. Results are favourable, with HEMTs produced on 150 mm wafers exhibiting a two-terminal gate-to-drain breakdown in excess of 90 V, which is comparable to equivalents fabricated from 100 mm wafers. At a drain-source voltage of 10 V, transistors formed on 150 mm wafers have an average normalized maximum drain current of 1,124 mA/mm, a peak transconductance of 372 mS/mm and pinch-off voltage of -3.1 V.

Compared to devices formed on 100 mm wafers, drain current and transconductance are superior by about 5 percent, and pinch-off voltages are very similar (see table 2). The specification yield for these three DC parameters is 100 percent, as measured on 30 sites across the 150 mm wafer. Somewhat unexpectedly, switching fabrication from 100 mm to 150 mm wafers actually led to improved uniformity for some DC characteristics, such as maximum drain current and transconductance. We attribute this to the enhanced starting wafer uniformity and quality, plus the improved process control of the 150 mm fabrication line.


Table 2: Comparison of key DC parameter values and uniformity, 150 mm versus 100 mm at Vds of 10 V. 

Results of pulsed current-voltage characteristics are also encouraging, with devices formed on 150 mm wafers giving similar levels of performance to those made from 100 mm material. Pulsed current uniformity and device yield are excellent, according to GaN HEMT pulsed current-voltage characteristics across a full 150 mm GaN-on-SiC wafer (see Figure 4).


Figure 4: Mapping of 0.2 µm GaN HEMT pulsed current-voltage characteristics across a 150 mm wafer, pulsed at Vg = -5V, Vds = 30 V.  Excellent pulsed current uniformity and device yield are observed.

Development of affordable GaN MMICs will enable the fielding of advanced electronic warfare systems on aircraft such as the F15. Credit: US Air Force

Comparisons of output power and power-added efficiency at 4 GHz for wideband GaN MMIC power amplifiers formed on 150 mm and 100 mm wafers are also favourable (see Figure 5), with the larger format leading to marginally better performance and a tighter distribution. RF spec yield is also better, rising from 70 percent to 76 percent, according to full on-wafer RF testing.


Figure 5: RF performance (Pout and power-added efficiency) comparison for a wideband (0.5-5 GHz) MMIC power amplifier fabricated on 100 mm and 150 mm wafers. Comparable performance (slight improvement in PAE), somewhat tighter distributions and higher RF spec yield have been observed for early 150 mm wafers. Data shown was taken at 4 GHz with 28 V Vds.

Lastly, MMIC final-visual-yield has increased with the migration to larger wafers, rising from 85 percent to 95 percent. We expect this improvement stems from the reduction in manual wafer handling resulting from the use of automated 150 mm equipment, and we note that it is consistent with improvements we saw after transitioning our 75 mm GaAs MESFET and PHEMT processes to 150 mm wafers.

The improvements in visual yield, along with the higher proportion of devices meeting RF criteria, has culminated in overall chip yield per wafer rising from 59.5 percent to 72.2 percent for the MMIC example shown. This exceeds the assumption made for Table 1 that 100 mm yield would be simply maintained at the same level on 150 mm wafers, and makes an even more compelling argument for the improvement in affordability wrought from scaling. This will help to cut the cost of GaN MMICs, and should spur their uptake in various defence applications at many important frequency bands that the 0.2 mm gate length GaN process targets.

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