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Increasing The Availability Of GaN HEMTs

A robust, reliable foundry process will spur a proliferation of GaN applications

Automation on WIN’s GaN-on-SiC wafer processing line

BY WALTER WOHLMUTH, WEI-CHOU WANG, I-TE CHO AND WEN-KAI WANG FROM WIN SEMICONDUCTORS

The tremendous amount of money poured into the development of GaN RF and power devices is enabling new markets and driving an upheaval in existing ones. Thanks in part to governments around the world funding a variety of projects – including US initiatives such as DARPA’s Wide Bandgap Semiconductors for RF and AFRL’s title III GaN-on-SiC programme, plus the European effort KORRIGAN and the Japanese project NEDO – this technology has matured significantly.

GaN technology is now at a comparable maturity level to the GaAs technologies of the late 1990s, prior to the explosive growth in that industry. This was driven by commercial opportunities requiring higher data transmission and better efficiency.

The commercial opportunities for GaN include wireless communication. The traditional transistor deployed in base stations is silicon LDMOS, but migration to 4G LTE and HSPA networks sporting higher bandwidths has triggered a move to GaN HEMTs combining higher efficiency, higher bandwidth and reduced cooling requirements with a comparable price at the system level. This trend is set to continue, as base station products formed with GaN deliver the requirements for 4G communications while offering excellent reliability.

Other opportunities for GaN in the RF arena include a class of satellite communication known as VSAT, which is moving towards a more complicated, data-intense transmission technology referred to as the 4096 QAM format.

There are also changes in cable TV transmission technologies that are playing into the hands of GaN, as operators move to OFDM transmission on both up and downstream paths, due to the implementation of DOCSIS3.1 specifications that have a higher bandwidth in order to serve video-on-demand and HDTV.

And it is not just silicon LDMOS that is under threat from GaN – this material could also displace archaic, staid technologies such as travelling-wave tubes
and magnetrons used for microwave heating and phased array radar. In today’s microwave ovens, heating is extremely inefficient, imprecise, and
bulky, and introducing GaN could address all these weaknesses. Meanwhile, a switch to GaN in radar system architecture could trim weight and cooling needs, benefits that are highly welcome in the field of avionics. What’s more, GaN devices could replace travelling wave tubes for phase shifters.

GaN will also start to displace GaAs in some applications. Low-noise amplifiers based on GaN are more rugged than their GaAs counterparts, so circulators or isolators can be removed from the antenna path. Meanwhile, for power amplification, GaN delivers more power per unit area. 

Why WIN?

To address all of these markets, WIN Semiconductors is offering a comprehensive portfolio of GaN technologies from sub-GHz to 40 GHz, including power amplifiers, low-noise amplifiers, RF switches and passive components. Our flexible and open foundry approach enables these technologies to be optimized to meet customer needs. In addition, they can be paired with our extensive GaAs technology, allowing customers to enjoy the best of both worlds.

Another advantage that we have is that we can apply lessons to GaN manufacturing that we learnt from increasing our GaAs manufacturing volume, which is upwards of 24,000 150-mm wafers per month. This provides us with a competitive edge for cycle time, customer service and support, breadth of technologies, and competitive prices due to economies of scale.

If GaN devices are to become a mainstream, mass production technology, long-term demand for them will only exist if they can be manufactured in a manner that yields stable, reliable and repeatable products. Significant progress has been made by material suppliers, leading to better-quality semi-insulating SiC substrates with fewer defects and greater consistency.

This has been backed up by advances by suppliers of epitaxial growth services, with improved material quality enabling a stable supply chain. Thanks to these breakthroughs, optimising device processing is quicker than ever, because experiments produce far fewer ambiguous results, so learning is now very fast.

In comparison, GaN-on-silicon technology is not as mature. High defect densities impact material quality and repeatability, and there are also issues associated with excessive wafer warpage and losses associated with large edge exclusion zones. All of these are induced in part by the large lattice mismatch between GaN and silicon.

As well as these material issues, there are drawbacks in device design with GaN-on-silicon. Most high performance GaN RF power amplifiers require low resistance and low inductance source vias. Backside via formation can be challenging once the silicon substrate is thinned due to excessive warpage. The thermal conductivity of silicon is inferior to that of SiC resulting in electro-thermal performance issues for GaN-on-silicon devices that limit the power density of the transistors.

Power switching devices are less affected by this, because they generate far less heat under normal operating conditions than their RF counterparts. What’s more, power devices don’t tend to include backside source vias, simplifying backside wafer processing and reducing cost. Consequently, GaN-on-silicon technology is predominantly used in the power switch market, where it gives little away in performance to GaN-on-SiC, but is cheaper. In contrast, in the RF market there is a premium placed on performance and reliability, so GaN-on-SiC reigns supreme. Note, however, that there are niche opportunities for GaN-on-SiC for power switches, with the greatest chance of success in applications requiring blocking voltages in excess of 600 V.

Figure 1: WIN has a GaN process involving damascene T-gates with overlying source-coupled field plates to control the electric field distribution. A thick 4 μm air-bridge enhances current handling capabilities and provides high-Q inductors.

Device manufacture

We sub-divide the engineering of our transistor into five main areas: epitaxial design on SiC substrates, dielectric engineering, metallurgical engineering, electro-thermal design, and interface engineering. Many groups around the world have investigated these topics in detail, leading to a vast body of published literature on every one of these subjects. Insights are offered in the form of patents and papers, and we undertook a painstaking analysis to manoeuvre around existing IP.

High-voltage handling and high output power of the transistors is possible through the use of a damascene T-gate and an overlying source-coupled field plate. Minimal charge trapping and dispersive effects result from interface and dielectric engineering, enabling good, stable and repeatable device performance.

We offer a portfolio of transistor technologies, with different gate lengths and breakdown voltages. Devices formed with our 0.15 μm and 0.25 μm processes are engineered to operate at 28 V, and have a minimum breakdown voltage of 70 V. Meanwhile, the GaN HEMTs fabricated with our 0.50 μm process are designed to operate at 50 V and have a minimum breakdown of 130 V (see Figure 2).

 

Figure 2: DC performance on the 0.50 μm GaN-on-SiC process. The Ids-Vds curve records operation to 60 V for the nominal 160 V breakdown voltage process. The plot reveals good sub-threshold characteristics and high Ion/Ioff ratio for a compound semiconductor technology.

In our case, the interconnect and passive component architecture for the GaN MMIC processes has been leveraged from our GaAs MMIC technology, but modified primarily for higher operating voltages. Circuits are constructed with high-performance, edge-lifted ELC MIM capacitors, thin film resistors, and high-Q inductors that are commonly deployed in our GaAs technology. This creates a GaN technology that features a robust MMIC process with a 4 mm-thick air-bridge metal and 1 μm-thick global interconnect metals.

Automation on WIN’s GaN-on-SiC wafer processing line.

We were able to draw on our expertise as the world’s largest manufacturer of GaAs devices to re-engineer the back-side processing of GaN-on-SiC HEMTs, rather than following the approaches our competitors. Our efforts led to the development of a highly manufacturable process technology that includes: high-speed etching through SiC and then GaN-based materials; improved wafer mounting media involving specialized bonding wax and substrates; handling of by-product formation during high-speed etching and subsequent, repeatable removal of by-products; and back-side seed layer optimisation for good adhesion and conformal coverage in 100 mm deep vias with a width of less than 30 μm (see Figure 3 for a 30 μm x 60 μm oval substrate via that connects back-side metallization to the front-side source of the transistors).

 

Figure 3: Scanning electron microscopy cross-section of a transistor with an integrated source backside for low-source inductance and resistance connections. A 30 μm x 60 μm oval substrate via connects backside metallization to the front-side source of the transistors. The T-gate is visible adjacent to the source pads on the bottom of the figure. Note that the divot inside the substrate via is potting material used to prepare the sample before SEM imaging.

Additional aspects of our processing technology include improvements in regards to demounting of a highly stressed thinned wafer; high-speed sawing with minimal chipping of an extremely hard SiC material system; optimisation of tape materials to provide environmentally-friendly, green material usage; and care to control interactions between all of these many processes.

Using this approach, we produce devices that deliver high-efficiency RF performance. By reducing source inductance and resistance, our HEMTs provide stable linear gain at low input power and have good 3dB/decade compression. When delivering a 3 GHz, continuous-wave input signal at a 50 V bias, the output power exceeds 5.5 W/mm, power-added efficiency is greater than 60 percent, and linear gain is almost 19 dB higher than that produced with silicon LDMOS technology (see Figure 4).

 

Figure 4: RF performance on the 0.50 μm GaN-on-SiC process at 3GHz with Idq=10mA/mm and Vds=50V for a 1.25 mm device achieving more than 5.5 W/mm under continuous-wave conditions.

Reliability of our devices has been proven through extensive reliability testing that complies with many JEDEC specifications. By working in collaboration with researchers at the University of Bristol, Centre for Device Thermography and Reliability, we have accurately determined the junction temperatures for the devices during reliability testing and under normal operating conditions. One of the JEDEC specifications is associated with a DC high-operating-lifetime-test that forms a basis for evaluating the mean-time to failure (MTTF). Testing involved four sets of samples from the 0.25 μm GaN-on-SiC process, with devices driven until they failed at temperatures ranging from 331 °C to 369 °C. Curve fitting revealed an MTTF of 1 million hours and an activation energy of 2.1 eV for a peak channel temperature of 238 °C. These findings are in line with recent reports in literature (see Figure 5).

 

Figure 5: Mean-time-to-failure (MTTF) performance for the 0.25 μm GaN-on-SiC process. Activation energy is 2.1 eV and MTTF is 1 million hours at a peak junction temperature of 238 oC.

On its own, an excellent process for producing GaN HEMTs is of little value to designers – it needs to be backed up with a comprehensive process design kit providing accurate modelling and supporting data. We have met this need and offer a proprietary, scalable model that can simultaneously predict GaN HEMT performance under DC and pulse operating conditions, and provide a good prediction of large-signal characteristics (see Figure 6).

 

Figure 6: Model verification for one-tone characteristics at 10 GHz measured with 50 Ω termination for a 1.25 mm, 10 x 125 μm device. Good fit obtained for various quiescent Idq conditions. Note that symbols and lines represent measured and simulated data, respectively.

This model, which is supported in both Agilent ADS and AWR Microwave Office software platforms, also includes comprehensive passive modelling. This exploits our expertise in passive components, with the model modified for differences in substrate and epitaxial materials. Engineers that are armed with this toolkit and use our GaN fabrication services are well placed to tap into the many, growing opportunities for this wide bandgap transistor. During the next decade, it is sure to become the incumbent technology in many parts of the RF domain.


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