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Perfecting GaN-on-silicon Power Electronics

Inserting rare earth oxides increases material quality, trims wafer bow and boosts transistor performance


With electricity now accounting for a staggering 43 percent of primary energy consumption, according to the International Energy Agency, the benefits of efficient energy conversion – from both an environmental and an economic perspective – are bigger than ever. And this pay-off is only going to grow as more electrical systems are manufactured for deployment in electric vehicles,computer power supplies, solar cell inverters and power converters for LED lighting.

One area where the use of electrical systems will grow fastest is in electrical vehicles. Speaking on behalf of Ford at CS International 2014, Power Semiconductor Research Engineer Ming Su revealed that 25 percent of the company’s vehicles are expected to be electrified by 2020. Making the electrical conversion in these vehicles as efficient as possible will be high on the priority list of engineers based in the US, because this will help automobiles to satisfy a government mandate for 2025 that demands a fuel efficiency of at least 54.5 miles per gallon.

Thanks to its low cost, widespread availability and familiarity, silicon has been the semiconductor of choice for many years in electrical systems, where it is used to perform various roles, including voltage conversion. However, judged purely in terms of performance, this incumbent is inferior to wide bandgap semiconductors, such as SiC and GaN.  Switch from silicon to GaN and it is possible to construct devices that combine a low on-resistance with
a low parasitic capacitance, culminating in low power losses when the device is on and when it is switching between states.


These great attributes, which stem from the use of a high-mobility two-dimensional electron gas at the interface between the GaN and AlGaN layers of a HEMT, make this class of transistor a promising device for incorporation into switched-mode power supplies serving many of the applications outlined above. According to the GaN power semiconductor manufacturer EPC of El Segundo, CA, 600 V devices account for a quarter of the overall power transistor market, with devices rated at 200 V or below pulling in three-quarters. Since GaN HEMTs are capable of covering all these voltages, there is good reason to believe that this wide bandgap semiconductor can be adopted in a broad range of power conversion applications.  

Foundations for GaN

Ideally, manufacture of GaN HEMTs would involve growth on a native substrate. However, GaN substrates are prohibitively expensive and limited in size and availability, so different foundations must be used. The most common alternative, silicon, enables the fabrication of GaN HEMTs that are competitively priced compared to the incumbent. However, the penalty to pay for growth on silicon is that the production of these devices is far from easy. Engineers don’t just have to contend with bow of the epiwafers, caused by differences in lattice constants and thermal expansion coefficients – there are also challenges related to unwanted chemical reactions at the silicon surface.

One unwanted reaction is that of silicon with ammonia to create SiN. This resulting nitride can grow in an amorphous manner, destroying the crystal registration and with it the quality of the overlying GaN. Turning to a gallium wetting-layer is not a viable solution, because silicon is soluble in liquid gallium, so defects arise from the meltback of gallium. This doesn’t occur with aluminium, the only alternative wetting material, but in this case the growth conditions have to be carefully controlled to minimise eutectic-driven diffusion of silicon into the upper GaN layers. And if there are any imperfections in the quality of AlN, such as pinholes, GaN can make contact with silicon, leading to meltback defects or silicon diffusion into GaN.

To avoid all of these issues, our team at Translucent of Palo Alto, CA, has pioneered the development of an engineered buffer that aids the transition between silicon and GaN, and returns full design freedom to MOCVD process engineers. Our buffer is an insulating, single-crystal rare-earth-oxide (REO), with a composition carefully chosen to be lattice-matched to the silicon on its lower surface. Meanwhile, an upper surface is engineered so that defect growth is quite dissimilar to that associated with GaN on silicon – and more like that of GaN on sapphire − thanks to the GaN lattice being more closely matched to its foundation.

Benefits of the REO are not limited to lattice matching: this layer is also chemically inert, so it provides a physical barrier to silicon diffusion. Consequently, it is not possible for gallium to come into contact with silicon. What’s more, epistructures grown with our engineered substrates can maintain a high degree of lattice registration, because the REO is lattice-matched to the silicon substrate. Note that the top interface between GaN and the REO is chosen to have a small mismatch, because this softens the interface and provides a degree of compliance.

Benefits of the oxide

Turning to an REO offers a new route to the production of epiwafers with a very low bow, which is a pre-requisite for processing in silicon lines. We can manage bow by pre-straining the wafer. Prior to MOCVD deposition of GaN, we make the wafer dome shaped. Without this, the MOCVD process would naturally result in wafers that are bowl-shaped – but thanks to the pre-straining, we are left with epiwafers that are very flat (see Figure 1, which shows a selection of wafers that have been measured, post REO growth, using a three-dimensional optical profilometer).

Figure 1: It is possible to control the bow using REO layers. The plot second from the right is a silicon wafer prior to any depositions. Bow measurements are taken using an FRT MicroProf 3D optical profilometer

By adopting this approach, GaN epiwafers with an REO layer can be flat enough to be compatible with steppers used in microlithography. The requirements originate from the depth of field of the optical system in the stepper, and are defined in terms of maximum bow by SEMI. Wafers with a diameter of 100 mm, must have a bow below 40 mm, while those that are 150 mm and 200 mm across must have bows of less than 60 mm and 65 mm, respectively.

Improvements in device performance also result from inclusion of an REO. This oxide is an insulator, so it increases the transistor’s breakdown voltage. In addition, a common failure mechanism is addressed: devices often breakdown due to silicon diffusion, but this can’t happen when an REO is involved, because this oxide provides an impenetrable barrier to silicon atoms.

To mitigate this diffusion process when producing conventional devices, thicker GaN layers are required. This adds to production costs, and must be weighed against the expense associated with deposition of a REO layer. Note that the insulating nature of this oxide means that it also reduces the thickness of GaN required to hit a particular blocking voltage. We anticipate that by preventing diffusion and aiding device robustness to high voltages, we may be able to trim the GaN thickness by at least 25 percent and also potentially remove all of the interlayers. These actions could result in a significant cost saving associated with device production.

A further benefit of our technology is that it is considerably different from other techniques for forming GaN-on-silicon, giving it an enviable position in terms of intellectual property. IP ownership is increasingly viewed as an important asset as the industry matures: Indeed the French market analyst, Yole Développement, recently produced a market report dedicated exclusively to GaN-on-silicon IP, underlining the importance of proper IP protection.

Promising results

Experimental results on epiwafers and HEMTs back up our claims of the virtues of our REO-based technology for GaN-on-silicon transistors. These efforts included a side-by-side comparison of a 100 mm silicon wafer, and our engineered, REO-based template that had been pre-strained to offset the stresses from MOCVD deposition. These wafers were placed in adjacent pockets in an MOCVD run conducted using a standard sapphire process for the production of 2 DEG HEMT structure. After growth, the epiwafer with the oxide interlayer had less than one-quarter of the curvature of the structure grown on bare silicon, and with a bow of just 14 mm, the epiwafer with the REO layer was comfortably within spec for processing in a silicon line (see Figure 2). In contrast, the GaN-on-silicon wafer was significantly out-of-spec.

Figure 2: MOCVD bow during growth. This trace shows the curvature of two wafers on the same platen in a run. One was a bare silicon wafer and the other an REO template. In-situ monitoring of the entire process is via a LayTec EpiTT system that records the true wafer temperature, curvature, and reflectivity signals at 450 nm and 633 nm. These tools monitor the evolution of the GaN surface and the quality of the bulk GaN growth throughout the growth process. The start of the MOCVD run is at time = 0, and growth occurs up to 3800 s at which point the wafer begins to cool and tensile bowing starts. When unloaded after 6400 s, the two-dimensional electron gas on the silicon wafer has a curvature of 106/km, where as that grown on the REO template has a curvature of only 11/km. A curvature of 106/km corresponds to a bow of 133 µm, which is out of spec, where as a curvature of 11/km corresponds to a bow of only 14 µm, which is comfortably within spec for this sized wafer.

By turning to AlN interlayers, it is possible to reduce the bow and manage defect propagation in GaN-on-silicon HEMTs. These AlN layers can also be used within our structures, but we plan to work to reduce and even eliminate them, because we expect the REO to take over much of this functionality (figure 2 shows how an REO layer can be used to bring a process that is out-of spec, to being comfortably within spec, in terms of wafer bow).

Impenetrability of the REO layer to silicon diffusion is proven with a combination of transmission electron microscopy and energy dispersive X-ray analysis of a structure with layers of GaN, AlN, and ErO on top of silicon (see Figure 3).  According to the X-ray analysis, there is no trace of silicon in the GaN layer. In addition, no oxygen or erbium is found in the GaN, indicating that the REO does not act as a source of contamination.

Figure 3: Transmission electron micrograph and composition analysis demonstrates that a rare-earth oxide layer can provide an impenetrable barrier to silicon diffusion.

Figure 4: X-ray diffraction uncovers the components of an REO template and GaN 2DEG HEMT structure

High crystal quality of the HEMT structures formed on our engineered templates is revealed in X-ray diffraction plots, which feature relatively sharp AlGaN fringes. The widths of the X-ray peaks can determine dislocation densities in the epitaxial structure, according to the work of Detlef Hommel and co-workers from the University of Bremen.

Values of 600 arc seconds for the (002) reflection and 1400 arc seconds for the (102) reflection suggest that the dislocation density in the GaN layer is 2 x 1010 cm-2. In our view, this value is perfectly respectable, and provides further validation that our template provides a good foundation for the subsequent MOCVD growth of GaN.

Another great attribute of our REO layer is that it leads to a growth mechanism that is the same as that for GaN deposited on sapphire, which is the most common substrate for GaN growth, but one that is unsuitable for electrical devices, due to its insulating properties. Mapping of the surface of GaN grown on REO by atomic force microscopy reveals the presence of parallel atomic steps, indicating that two-dimensional step-flow growth occurs – just like it would on sapphire (see Figure 5).

Figure 5: Atomic force microscopy reveals the characteristic step-flow morphology. The z-range is 4.2 nm and the RMS 0.51 nm (MOCVD courtesy of

The quality of the underlying undoped GaN was independently evaluated via Hall measurements – an n-doped GaN calibration layer doped to 1.1x1018/cm3  had a measured mobility of 250 m2 V-1s-1.

Device results

Using a modified GaN-on-sapphire MOCVD process, HEMT device layers were grown on Er2O3-on-silicon (111) templates. An AlN buffer layer was grown on the Er2O3, followed by a thick GaN layer, a 3 nm AlN interlayer, an 30 nm-thick barrier layer of Al0.25Ga0.75N and a 1 nm GaN capping layer. Throughout the MOCVD run, laser reflectometry and emissivity corrected pyrometry monitored the growth of the nitride layers.

The finished wafers were processed using a standard interdigitated source and drain design (with no field plates) and employed all of the standard processing steps such as BCl3/Cl2 reactive ion-etching and deposition of gold-free contacts that are common to today’s GaN-on-silicon FETs.

Typical results for the completed generic device are given in Figure 6. The results confirmed that this new approach for making III-N power FETs on silicon using an REO buffer is a viable alternative to other methods commonly used to deposit GaN on silicon. We demonstrated that, using standard MOCVD processes, devices with perfectly reasonable performance can be made.

Figure 6: A photomicrograph of a typical device layout is shown for processed GaN-on-REO-on-Si FET that yields the following results: A drain current of 800 mA/mm, a channel mobility of 920 cm2 V-1s-1, a channel sheet carrier concentration of 1.36×1013 /cm2 and sheet resistivity = 496 W/sq. (Device processing: Rick Brown,

Indeed, these devices have a performance that is equivalent to those shown by similar devices not grown on-top of the REO. Additionally, we have demonstrated complete MOCVD design freedom over the available MOCVD processes that can be used because of the chemical and physical properties of the REO layer.

What’s next?

We can produce REO templates with diameters of 150 mm and 100 mm, and we are presently ramping-up our 200 mm REO production in our facility. Allied to these efforts, we are engaging with customers and promoting REO templates as a genuine alternative to the step-graded and superlattice approaches that are more commonly employed today.

During these conversations, we are pointing out that our REO material can take on the role of a gate dielectric on top of an MOCVD structure, thanks to its high dielectric constant of 12 to 15.

Our REO-based templates are not limited to serving the power electronics markets − they are attractive options for the production of LEDs and RF devices. One way that these REOs can aid LEDs grown on silicon is by introducing a mirror beneath the active region that stops light from being absorbed by the substrate.

This insertion of a distributed Bragg reflector, however, is not the only role that an REO can play – it can also allow the introduction of the more common orientation of silicon, silicon (100), into the LED industry. Deposition on this orientation of silicon is potentially very useful, because it enables the growth of non-polar and semi-polar GaN, which can lead to higher efficiencies at longer wavelengths, thanks to either the reduction or elimination of energy-sapping internal electric fields.

This opportunity for REO-based templates, alongside their tremendous promise in power electronics, shows that there are multiple benefits to inserting an oxide layer between silicon and GaN. We hope that many will look to pursue this route, and allow us to play a significant role in helping this industry to make better compound semiconductor devices.


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