Addressing The Weakness Of GaN Transistors

Researchers reveal how to slash dynamic resistance, minimise interface traps and identify the origin of current collapse. BY RICHARD STEVENSON


There is no doubt that the GaN transistor has tremendous promise. Sales of this device, which can act as a switch in the likes power supplies, solar invertors and electric vehicles, are tipped to eclipse $1 billion before the end of this decade, according to market analyst Yole D�veloppement.

However, it is by no means guaranteed that sales will soar to anything like that level. Today, this GaN transistor has several weaknesses that have to be addressed before commercial success can follow. Although the static on-resistance (RON) of these chips is superior to those of equivalent silicon devices, dynamic resistance is often much higher than that of the incumbents, and this severely compromises the overall performance of these wide bandgap transistors. Meanwhile, a less common but very promising form of the HEMT – that incorporates a metal-insulator-semiconductor (MIS) gate structure and has a lower leakage – has a number of shortcomings. The MIS-HEMT is plagued by threshold-voltage instability and a condition known as current collapse: a temporary increase in RON after high-voltage off-state biasing that arises from off-state trapping.

Insights into all of these issues and more were provided at the recent International Electron Devices Meeting (IEDM), which was held from 9-11 December in Washington DC. At this gathering, a team from FBH Berlin revealed how the dynamic RON in a GaN HEMT can be slashed by several orders of magnitude; researchers at The Hong Kong University of Science and Technology reported new insights into interface-induced instability in the threshold voltage of MIS-HEMTs; and a partnership between MIT and Texas Instruments explained why Zener trapping is the origin of current collapse in this class of transistor.

Dynamic improvements

Many have argued that the superiority of the GaN transistor over its silicon rival is captured in a figure of merit for switching efficiency: the product of on-state resistance and gate charge. Compared to commercial silicon devices, many GaN HEMTs made by industry and academia have an RON� that is typically an order of magnitude lower. Unfortunately, such claims of supremacy neglect the difference in the dynamic on-resistance of silicon and GaN devices. “If, for example, you have a 600 volt switching device, and you have an improvement in the static RON� by a factor of ten [by moving from silicon to GaN], but at the same time you will worsen the dynamic switching RON� by a factor of a hundred, there is no use in that," points out Hans-Joachim W�rfl from FBH Berlin.

This has led a growing number of GaN developers to take increasing interest in the dynamic resistance of their devices. Resistance tends to have a high value due to temporary charge trapping, which is one consequence of switching. Negative charge trapping often occurs close to the channel, near to the drain-side-edge of the gate. The flow of electrons through the channel is impeded until the trapped charges are emptied, leading to increased conduction loss and compromised system efficiency.

At IEDM, W�rfl detailed approaches for realising a dynamic RON� that is comparable to a static RON in GaN HEMTs designed for switching at 500 V. “That was not imaginable a couple of years ago, when we had a factor of thousand [difference in dynamic and static RON ]."

A study of various HEMT structures uncovered refinements to the device architecture that can slash dynamic RON. To perform this investigation, engineers fabricated a range of GaN transistors on n-type SiC with differing buffer compositions. Normally off devices were fabricated using p-GaN gate technology and had a gate length of 1.2 �m, while normally on variants were based on a 0.7 �m Ir/Ti/Au gate technology. All devices were passivated with benzocyclobutene layers, and to prevent spurious vertical leakage and boost yield, source and drain fingers were additionally isolation-implanted at their centre (see Figure 1).

Figure 1. GaN-based high-voltage switching devices developed at FBI. The normally on and normally off devices are fabricated using the same technology, with the exception of the gate module. The inset show�details related to the p-type GaN technology, which renders the devices normally off

W�rfl believes that if the improvements to dynamic RON are to be worthwhile, they must not come at the expense of a severely compromised breakdown voltage per micron: “The breakdown strength tells you how large you can make the gate-drain distance. Of course, you would like a very small, safe, gate-drain distance, because if this is very small, the static on-state resistance is decreased."�

The requirement for a high electric field strength that allows a shorter gate-drain separation rules out doping the buffer with iron and adding an AlGaN buffer: dynamic RON is reduced with this approach, but the breakdown strength is just 40 or 50 V/�m, about a third of what is theoretically possible. Simply doping the buffer with carbon is also inappropriate, because although this boosts breakdown strength, it also increases dynamic RON.

To realise a high field strength and a low RON, the team from FBH has drawn on both of these approaches. Its best test structure features a graded AlGaN barrier with an average aluminium concentration of 5 percent, which is positioned close to the channel, and a carbon buffer that is doped to�4 x 1018 cm-3 and inserted underneath regions that are not prone to large field changes during switching. With this carefully selected combination, HEMTs that switch at 500 V can exhibit a breakdown field strength of 80 V/�m and a produce a dynamic RON that is just two-and-a-half times that of static RON.

Time dependency measurements reveal that immediately after switching from the off-state, the dynamic RON� of the HEMT decreases rapidly, before flattening out and getting fairly close to its static value after 100 �s. Decline in dynamic RON� is not exponential, but can be fitted by multiple exponential functions, suggesting that several different trap states are contributing to charging and discharging within the device.

W�rfl and his co-workers are now trying to make further improvements to dynamic RON. This effort forms part of a project involving a large European company, which requires further gains to deliver a competitive product. “Otherwise the difference between [GaN HEMTs and] the very-good-performing silicon is getting smaller and smaller, and there would be a question whether someone would pay the higher price, even if it were for GaN-on-silicon," says W�rfl. The team also hopes to increase the breakdown strength of its devices. “I think we could go to 120 V per micrometre," says W�rfl, who believes that this is realistic while maintaining the value for dynamic RON� achieved in HEMTs with a breakdown of 80 V/�m.

Interface traps

For high-voltage power switches, the MIS-HEMT is favoured over the more common Schottky-gate HEMT because it is capable of delivering a lower gate leakage current and an enlarged gate swing. However, this more promising class of transistor tends to be plagued by a high density of traps at the interface between the dielectric and the III-N. The dynamic charging and discharging of these traps has been blamed for instability in the transistor’s threshold voltage. To address this issue, engineers from The Hong Kong University of Science and Technology have developed a deposition process that yields a high-quality interface. “We believe that we have gotten to the heart of the problem and developed an effective solution," claims team-leader Kevin Chen.

At IEDM, this group unveiled its deposition process for forming a MIS structure, and also detailed a new approach to characterising the interface traps in MIS-HEMTs. The latter is a tricky task, due to the presence of two interfaces: that between the dielectric and III-N, and that between AlGaN and GaN.

Chen’s team form a high-quality MIS structure by employing an in-situ, low-damage remote plasma treatment to remove the native oxide and add a nitridation inter-layer. After this, they deposit a gate dielectric. Components of the plasma,�NH3-Ar-N2, perform different roles: NH3-Ar removes the native oxide, while the N2 enables deposition of the nitridation inter-layer. On top of this, engineers deposit, in-situ, a 25 nm-thick layer of Al2O3, before the entire structure is annealed at 500 �C under oxygen.

Interface traps in the MIS-HEMTs were uncovered by analysing the frequency- and temperature-dependent onset of the second slope in the current-voltage characteristics. Using frequencies varying from 400 Hz to 10 MHz and temperatures from ambient to 200 �C, engineers determined an interface trap density of�1012 – 1013 cm-2 eV-1.

Monolithic circuits

In a separate paper presented at IEDM, Chen and his co-workers claimed the first demonstration of a form of GaN-based high-voltage start-up circuit – one with low standby-power consumption and designed for off-line switch-mode power supplies. This mode of power supply is used in personal computers, battery charges, central power distribution systems, consumer electronics and LED lighting.

To form their monolithic circuit, the engineers used E-mode and D-mode HEMTs, rather than the more conventional Schottky-gate HEMTs (see Figure 2). According to Chen, two of the strengths of the E-mode MIS-HEMT over its conventional cousin are: a larger positive threshold voltage that enables enhanced electromagnetic interference immunity; and a larger gate swing, which increases the compatibility with existing silicon-based gate driver ICs. The D-mode MIS-HEMT also has its merits, being more suitable than a conventional equivalent for the large negative threshold voltage – typically -5 V or more – needed in the start-up circuit.

Figure 2. Engineers at The Hong Kong University of Science and Technology have produced monolithic integrated circuits with E-mode and D-mode MIS-HEMTs

The epitaxial structure used for making the 600 V MIS-HEMTs for the IC was deposited on silicon and contained a�21 nm-thick GaN/Al0.25Ga0.75N/AlN barrier layer and a 3.8��m-thickGaN buffer. Device fabrication involved electron-beam evaporation of Ti/Al/Ni/Au source and drain contacts, deposition of an AlN/SiN passivation layer and planar isolation of active regions by fluorine ion implantation. After opening the gate window, ions were applied to the gate region of E-mode devices. This was followed by the NH3-Ar-N2 plasma treatment process previously decsribed, deposition of a 17 nm-thick film as the gate insulator, and the addition of a Ni/Au gate electrode.

Chen says that one of the highlights of the team’s device technology is its passivation process, which leads to effective suppression of current collapse and a very small dynamic on-resistance. E-mode MIS-HEMTs have a high threshold voltage of 3.6 V and a large gate swing of 14 V, thanks to integration of fluorine implantation, surface nitridation and the gate dielectric processes. Supplied with an input of 200 V, the power supply circuit (see Figure 3) has a start-up current of 1.07 mA, a start-up time of 65 ms (with a 10 �F output capacitor), and a stand-by power that is calculated to be 2.1 mW. “The performance is comparable to a silicon-based circuit in terms of the start-up current and standby power consumption," says Chen.

Figure 3. The switch mode power supply produced by the team at The Hong Kong University of Science and Technology contains three GaN MIS-HEMTs

According to him, the ultimate goal for his team is to build a circuit with GaN for a highly efficient, compact, off-line switch-mode power supply. “The hysteresis comparator in the start-up circuit can be achieved using GaN E/D-mode HEMTs or MIS-HEMTs, which has not been done in this work yet." If the circuit is to demonstrate commercial viability, it must also pass reliability tests involving operation under extreme conditions for lengthy periods.

Zener trapping

The weakness referred to as current collapse, the temporary increase in a GaN transistor’s RON after high-voltage off-state biasing, is known to result from excessive trapping. Its precise origin, however, has been something of a mystery – but it is starting to unravel, with a team from MIT and Texas Instruments claiming at IEDM that current collapse stems from high-field, tunnelling-induced electron trapping. These researchers studied this phenomenon in AlGaN/GaN MIS-HEMTs with a breakdown voltage greater than 600 V. Devices were fabricated from a 6-inch III-N-on-silicon epiwafer supplied by a commercial vendor.

Step-stress measurements were made on these transistors by increasing the drain-source voltage by 20 V every 10 s. Linear drain current, which is inversely proportional to RON, degraded by about 10 percent as the voltage approached 200�V, before abruptly dropping to 10 percent of its initial value. Further degradation occurred as the voltage was cranked higher, with the linear drain current becoming negligible and RON increasing by around 10 orders of magnitude. However, this damage is fully recoverable – initial device characteristics recovered with strong UV illumination or moderate thermal treatment, such as heating for 3 hours at 100 �C.

To increase the operating voltage of GaN MIS-HEMTs, many developers have turned to multiple gates that may also prevent current collapse – although their effectiveness to address the later issue is unclear. To try and resolve this, the US team investigated the influence of device geometry. They found that the lengths of the three field plates used in the transistor do not impact trapping characteristics.

A study of the dynamics of trapping followed, involving plotting of trapping time as a function of the reciprocal of the peak electric field, which occurs inside the AlGaN barrier and under the edge of the third field plate. The shape of this graph strongly suggests that the origin of current collapse is a valence-band-to-trap tunnelling process, which the team refer to as Zener trapping. Substitutional carbon on nitrogen sites is suggested to be a primary culprit. Team-member Donghyun Jin says that if carbon is to blame, it should be minimised in the GaN channel and AlGaN barrier to reduce Zener tunnelling. “However, its concentration in the buffer should be retained high enough to achieve high resistivity and a high level of breakdown voltage."

So, a delicate balancing act is recommended, just as it is to realise the combination of a high breakdown voltage and low on-resistance in conventional HEMTs. Optimising these trade-offs will take time, but progress may well be reported at papers given at the next IEDM, which takes place in December in San Francisco.

Devices made by FBI on SiC substrates

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