Anvil To Serve Up Cheap SiC Switches
In 2011, UK-based Warwick University launched Anvil Semiconductors to develop cheap but high quality SiC power semiconductor switches. Two years and some £2 million in funds later, the company has just won the National Microelectronics Institute Innovation in power electronics award and will soon deliver its first products.
Silicon carbide holds incredible promise as the material for tomorrow's power electronics applications. Devices are faster, more efficient and can withstand much higher voltages and currents than the straight silicon equivalent.
SiC Schottky diodes have pretty much replaced silicon p-n diodes in switched-mode power supplies for computers, while SiC transistors are making in-roads into hybrid and all-electric vehicle, photovoltaic applications and more. But despite rapid progress, cost is a major stumbling block. Anvil Semiconductors could make a difference.
The company has developed a process to produce SiC power switches at a similar cost to silicon by growing layers of SiC on silicon wafers instead of using expensive bulk SiC.
"Our essential cost reduction is substituting a $1000 4H SiC substrate with a $40 silicon substrate," states Anvil founder and managing director, Peter Ward. "We're [depositing SiC on] 100mm silicon wafers at the moment but will get up to 200mm wafers within our pre-production time-scales."
Today, the likes of Infineon and Cree are busy developing SiC devices based on 4H SiC crystalline materials. This polymorph is grown via PVT as a single crystal and then sliced to produce relatively defect-free wafers, up to six inches in diameter. However, the growth process is slow and energy-intensive, yielding very pricey substrates.
But a second polymorph could provide an alternative. In theory, layers of 3C-SiC could be grown epitaxially on silicon wafers as this polymorph has a cubic crystal structure just like silicon.
But while the resulting wafer could be produced much more cheaply than a 4H-SiC wafer, lattice mismatches and differences in thermal expansion coefficients between the 3C-SiC layers and silicon seed wafer induce in-plane stresses that cause wafer bowing. Device performance plummets and so manufacturers have stuck with the costly 4H-SiC wafers.
However, Ward, and colleagues, have developed a novel, low pressure CVD 3C-SiC growth process, that they claim bypasses these problems.
The Anvil Semiconductors team has been working with researchers at the University of South Florida to hone SiC device development and reactor technology.
Prior to SiC growth, a mask is placed over the silicon wafer to define structures in the scribe lines of the wafer. The team then deposits a one and a half micron layer of heavily doped, dislocated material onto the silicon seed wafer. This helps to relieve stresses from lattice mismatches that lead to wafer bowing, and also allows vertical conduction through the interface.
"This layer is doped with dopants from the silicon wafer and nitrogen, allowing us to conduct through the silicon carbide-silicon heterojunction," says Ward. "So we can conduct from the top to the back of the wafer and have built devices where you cannot see additional resistance at the interface. This makes us very competitive with GaN-on-silicon, which can't conduct vertically."
In the same run, monocrystalline SiC is then grown in the die areas between the scribe lines, with polycrystalline SiC forming in the scribe lines. As Ward says: "We are effectively interfering with the epi-process and producing polycrystalline SiC in the scribe lines while growing single crystalline epilayers where we want to build the device."
Crucially, the resulting mesh of polycrystalline SiC helps to relieve the thermal expansion differential stresses across the wafer that also lead to bowing.
"Instead of trying to fabricate a 100mm wafer, in terms of stress we are effectively making a 5mm die," he adds. "This makes our process very scalable and essentially independent of wafer diameter."
Indeed, as Ward highlights, his company is only limited to 100mm wafer sizes at the moment due to the industry's shortage of higher temperature, large wafer diameter epi-reactors.
"Silicon reactors typically run at 1000°C, but we need a reactor that has been designed to reach 1370°C and the only ones that exist have been built for [100mm] 4H SiC wafers," he explains. "So there aren't so many of these reactors right now but we know where they are and who they belong to, and we'veworked with most of these [organisations]."
Ward is also adamant the process is scalable to mass production, stating: " I have spent more decades than I would care to working with silicon, and having spent a lifetime manufacturing silicon devices, I see no reason why this shouldn't scale."
In the meantime, the Anvil team is busy building prototypes. A standard Schottky diode, similar to 4H-SiC versions but cheaper, is scheduled for release in 2014. And the company is also running a parallel MOSFET program, which could see prototype devices being released six months after the first Schottky diodes.
Ward won't talk about performance figures yet, only to say his team is pushing for very low on-resistance devices and is focusing on producing 650V Schottky diodes and MOSFETs. As he explains, using 3C-SiC on silicon, his team can fabricate a very cost competitive 650V device.
"Once we prove these 3C-SiC devices are a go-er we will start licensing commodity products," he adds. "We hope to stay as a niche product manufacturer but we see a very clear value chain from Schottky diodes to MOSFETs and probably to driver circuits as well."