Wolfspeed Expands SiC MOSFET Platform To 1200V
The new device simplifies designs and enables an increase in frequency while maintaining efficiency, lowering system cost, reducing circuit EMI and enabling 99 percent efficiency levels in three-phase power factor correction circuits.
These features enable designers of applications such as telecom power supplies, elevators, grid-tied storage, on and offboard EV charging, as well as factory automation to increase switching frequency while maintaining efficiency, decreasing system size and bill of materials.
“We are very encouraged about the new SiC products being introduced in new innovative discrete packaging," said Kurt Goepfrich, a Siemens hardware architect. “These new package options, such as the surface-mount 7L D2PAK, allow us to explore new topologies not possible with existing products available on the market today."
This device is claimed to achieve the industry’s lowest figure-of-merit for any SiC MOSFET at 1200V. Wolfspeed has released this device in a 4L TO-247 package and plans to release it in a 7L D2PAK in the coming weeks.
“SiC MOSFETs have proven to be beneficial for many high-power applications connected to a battery simply due to the improved efficiency." explains John Palmour, Wolfspeed’s CTO. “In the case where power is bidirectional, such as grid-connected AC-DC, the potential cost savings are significantly increased due to the reduction in the size of the input filter."
The device features Wolfspeed’s third generation C3M planar MOSFET technology, which engineers have already designed into various automotive and industrial applications. It features low on-resistance (75mΩ) combined with a low gate charge, making it ideally suited for three-phase, bridgeless PFC topologies as well as AC-AC converters and chargers.
The newly released packages allow engineers to take full advantage of the high-frequency capability of the latest Wolfspeed SiC MOSFET chips. The 4L TO247 package delivers a 3x reduction in total switching losses compared to a conventional TO-247-3 package.
The 7L D2PAK surface-mount package, specifically designed for high-voltage MOSFETs, practically eliminates the source inductance found in other packages and has a footprint 52 percent smaller than D3PAKs. This is made possible by the small die size and high-blocking capability of C3M planar MOS technology.
Designers can reduce component-count by moving from silicon-based, three-level topologies to simpler two-level topologies made possible by the improved switching performance.
These higher voltage SiC MOSFETs solve many of the limitations of silicon super-junction MOSFETs that make them impractical to use in two-level topologies. SiC has significantly lower output capacitance nonlinearity, making it possible to reduce the dead-time thereby minimizing total harmonic distortion at higher switching frequencies.